ERROR: Failed polling ready for burst read due to timeout = 5.0 sXL_易灵思FPGA21天前更新40 原因：可能没有用连续时钟采样 。或者时序质量问题，比如抖动太大或者幅度不对。
![图片[1]-ERROR: Failed polling ready for burst read due to timeout = 5.0 s-易灵思(Elitestek)论坛-FPGA CPLD-ChipDebug](\Users\15999645644\AppData\Local\YNote\data\1393024267@qq.com\b7ba05db23624844a4ab73162486bf6c\clipboard.png)
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