LiteX使用参考-Anlogic-安路社区-FPGA CPLD-ChipDebug

LiteX使用参考

https://jia.je/hardware/2023/04/24/litex-uart-over-jtag/

https://jia.je/hardware/2023/04/19/litex-digilent-arty-a7/

https://shzeng.cn/2023/05/07/litex/index.html

https://blog.csdn.net/weixin_46423500/article/details/129297000

https://www.taterli.com/9418/

https://zhuanlan.zhihu.com/p/454715624

https://zhuanlan.zhihu.com/p/598689675

FPGA工具链修改: ~/litex/python-litex/litex/litex/build/anlogic/anlogic.py

FPGA黑盒添加:/home/icmaker/litex/python-litex/litex/litex/build/anlogic/common.py

FPGA内部时钟及PLL添加:/home/icmaker/litex/python-litex/litex/litex/soc/cores/clock/anlogic_EG4.py

platform添加:/home/icmaker/litex/python-litex/litex-boards/litex_boards/platforms/icmaker_potato_pie_v4_20k.py

target添加:/home/icmaker/litex/python-litex/litex-boards/litex_boards/targets/icmaker_potato_pie_v4_20k.py

添加SDRAM:/home/icmaker/litex/python-litex/litedram/litedram/modules.py

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