【提问】LFE5U-85F-7BG381I LVDS输出信号幅度-Lattice-莱迪斯社区-FPGA CPLD-ChipDebug

提问LFE5U-85F-7BG381I LVDS输出信号幅度

lvds pin分配在bank 2; 

  1. 目前实测遇到的问题:输出(wire)27MHz时钟到lvds pin (P/N), 外接显示屏, 示波器测试的信号峰峰值 < 50mV;  远远小于 LVDS最低100mV要求

IOBUF PORT “TCLK_out” IO_TYPE=LVDS ;
IOBUF PORT “TA_out” IO_TYPE=LVDS ;
IOBUF PORT “TB_out” IO_TYPE=LVDS ;
IOBUF PORT “TC_out” IO_TYPE=LVDS ;
IOBUF PORT “TD_out” IO_TYPE=LVDS ;

LOCATE COMP “TCLK_out” SITE “J19” ;
LOCATE COMP “TA_out” SITE “H18” ;
LOCATE COMP “TB_out” SITE “F17” ;
LOCATE COMP “TC_out” SITE “D18” ;
LOCATE COMP “TD_out” SITE “C20” ;

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