通过TCL添加IO分配

如果要分配的IO比较多，也可以通过TCL来添加 IO分配。在interface界面通过Export Design和import Design来导出导入isf约束。

通过导出isf可以查看相关的语法,以下是导出的T20部分IO约束的语法。

Efinity Interface Configuration
# Version: 2023.2.307.3.17
# Date: 2024-04-23 12:11
#
# Copyright (C) 2013 - 2023 Efinix Inc. All rights reserved.
#
# Device: T20F256
# Package: 256-ball FBGA (final)
# Project: C12_logic_convert
# Configuration mode: active (x1)
# Timing Model: I4 (final)


# Device setting
design.set_device_property("1A","VOLTAGE","3.3","IOBANK")
design.set_device_property("1B_1C","VOLTAGE","3.3","IOBANK")
design.set_device_property("1D_1E","VOLTAGE","3.3","IOBANK")
design.set_device_property("3A_3B_3C","VOLTAGE","3.3","IOBANK")
design.set_device_property("3D_3E","VOLTAGE","3.3","IOBANK")
design.set_device_property("4A","VOLTAGE","3.3","IOBANK")
design.set_device_property("4B","VOLTAGE","3.3","IOBANK")
design.set_device_property("BR","VOLTAGE","1.2","IOBANK")
design.set_device_property("TL","VOLTAGE","1.2","IOBANK")
design.set_device_property("TR","VOLTAGE","1.2","IOBANK")
design.set_device_property("cfg","RECONFIG_EN","0","RU")




# Create instance
design.create_input_gpio("adc_data_in",13,0)
design.create_input_gpio("ram_addr",15,0)
design.create_output_gpio("ram_data_out",15,0)
design.create_output_gpio("acc_done")
design.create_input_gpio("acc_en")
design.create_input_clock_gpio("adc_clk_in")
design.create_input_gpio("adc_ora")
design.create_pll_input_clock_gpio("clk")
design.create_input_gpio("drive_switch_in")
design.create_output_gpio("drive_switch_out")
design.create_input_gpio("fifo_rst_in")
design.create_input_gpio("laser_fire_in")
design.create_output_gpio("laser_fire_out")
desin.create_output_gpio("laser_trig")
design.create_output_gpio("led0")
design.create_output_gpio("led2")
design.create_input_gpio("ram_cs")
design.create_input_gpio("ram_rd")

我们可以通过这种方式快速添加IO位置约束。