RISCV的中断处理-易灵思(Elitestek)社区-FPGA CPLD-ChipDebug

RISCV的中断处理

中断操作三个步骤:

1、中断初始化

void intr_init(){
//configure PLIC
//cpu 0 accept all interrupts with priority above 0
plic_set_threshold(BSP_PLIC, BSP_PLIC_CPU_0, 0);
//enable SYSTEM_PLIC_USER_INTERRUPT_A_INTERRUPT rising edge interrupt
#ifdef SYSTEM_AXI_A_BMB


plic_set_enable(BSP_PLIC, BSP_PLIC_CPU_0, SYSTEM_PLIC_SYSTEM_AXI_A_INTERRUPT, 1);
plic_set_priority(BSP_PLIC, SYSTEM_PLIC_SYSTEM_AXI_A_INTERRUPT, 1);


#endif
//enable interrupts
//Set the machine trap vector (../common/trap.S)
csr_write(mtvec, trap_entry);
//Enable external interrupts
csr_set(mie, MIE_MEIE);
csr_write(mstatus, MSTATUS_MPP | MSTATUS_MIE);
}

 

其中包括设置中断门限。相应中断的使能,以及中断的优先级,数字越大,优先级越高。然后还有中断入中数据的保存。

2、trap处理

void trap(){
int32_t mcause = csr_read(mcause);
//Interrupt if true, exception if false
int32_t interrupt = mcause < 0;
int32_t cause = mcause & 0xF;
if(interrupt){
switch(cause){
case CAUSE_MACHINE_EXTERNAL: axiInterrupt(); break;
default: crash(); break;
}
} else {
crash();
}
}

 

3、用户中断处理

void axiInterrupt(){




uint32_t claim;
//While there is pending interrupts
while(claim = plic_claim(BSP_PLIC, BSP_PLIC_CPU_0)){
switch(claim){
#ifdef SYSTEM_AXI_A_BMB




case SYSTEM_PLIC_SYSTEM_AXI_A_INTERRUPT:
bsp_print("Entered AXI Interrupt Routine, Passed!");
break;




#endif
default: crash(); break;
}
//unmask the claimed interrupt
plic_release(BSP_PLIC, BSP_PLIC_CPU_0, claim);
}
}

 

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