ERROR:Net clk100m drives a non-clock pin on block edb_top_inst/…-易灵思(Elitestek)社区-FPGA CPLD-ChipDebug

ERROR:Net clk100m drives a non-clock pin on block edb_top_inst/…

ERROR:Net clk100m drives a non-clock pin on block edb_top_inst/la1/GEN_PROBE[0].this_probe_p1[0]~FF.
: PLL output clock clk100m drives non-cldConsole panelERRORinverted.ERROR:Net clk5om drives a non-clock pin on block edb top inst/la0/GEN PROBE[2].this_probe_p1[o]~FF.ERROR
output clocks must be
:PLL output clock clk50m drives non-clock logic, Pll output clocks must be
inverted.ERROR: User Error: Found 4 errors while checking core interface requirements

 

20241022093933790-518788900bb662684db5292941dfbef

通过确认添加debug的信号发两点clk100m和clk50m也当作信号去采集,这是不对的。

20241022093952926-d8b7f76c2a42db045d9c077eb27a41d

 

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