ERROR : Cannot find netlist “top”. command: “add_ports”
ERROR : Failed to parse connection profile E:/FPGA_Demo/01_Ti60F100_DemoBoard/costumer/HDMI_rx__mipi_csi_tx/01_Ti60F100_hdmi_loop_demo_v4/debug_profile.wizard.json
ERROR : No top design. [EFX-0210]
周四 十二月 26 24 14:17:48 – C:/Efinity/2024.1/bin/efx_map finished. Exit code = 65 Exit status : Normal
Running Debugger Step 2 fail. See exit code and exit status
现象发生的原因是修改了project 模块名。而且程序内部在修改之前是已经添加过debug的,这种情况需要重新生成debug信号。
没有回复内容