显示器件管脚编号方法
器件未显示管脚编号
![图片[1]-Allegro PCB如何显示管脚编号-PCB设计社区-FPGA CPLD-ChipDebug](http://chipdebug.com/wp-content/uploads/2025/02/20250206182049776-91738837249.png?v=1738837249)
选择Display菜单下的Color/Visibility(颜色/可见性)或按设置的快捷键Alt+Ctrl+C
![图片[2]-Allegro PCB如何显示管脚编号-PCB设计社区-FPGA CPLD-ChipDebug](http://chipdebug.com/wp-content/uploads/2025/02/20250206182054557-61738837254.png?v=1738837254)
跳出如下对话框,选择Package Geometry选项→PIN_Number后打钩
![图片[3]-Allegro PCB如何显示管脚编号-PCB设计社区-FPGA CPLD-ChipDebug](http://chipdebug.com/wp-content/uploads/2025/02/20250206182055688-51738837255.png?v=1738837255)
设置后器件管脚就显示编号了,效果如下图
![图片[4]-Allegro PCB如何显示管脚编号-PCB设计社区-FPGA CPLD-ChipDebug](http://chipdebug.com/wp-content/uploads/2025/02/20250206182058760-31738837258.png?v=1738837258)
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Allegro provides a good and interactive working interface and powerful functions, and its front-end products Cadence, OrCAD, Capture, the combination of high-speed, high-density, multi-layer complex PCB design routing provides the most perfect solution.
Allegro has perfect Constraint Settings, users only need to set the wiring rules according to the requirements, and the design requirements of the wiring can be achieved without violating the DRC when routing, thus saving the tedious manual inspection time and improving the work efficiency!
It can also define parameters such as minimum wire-width or wire-length to meet the needs of today’s high-speed circuit board wiring.
Constraint Manger provides a simple interface for users to set and view Constraint declarations.
Its combination with Capture allows E.E. electronics engineers to set up regular data when drawing a circuit diagram and bring it with them to the Allegro working environment, where it can be automatically processed and checked when placing parts and wiring. The empirical values of these regular data can be reused for the same nature of the circuit board design.
In addition to the above functions, Allegro’s powerful automatic push and stick line and perfect automatic repair line function provide users with great convenience;
The powerful mapping function can provide multiple users to deal with a complex board at the same time, thus greatly improving the work efficiency.
Or use the optional graph cutting function to cut the circuit board into various blocks, so that each block has a full-time person at the same time to design, to achieve the purpose of the same graph design and can shorten the time course.
After renaming, online interchange and modifying logic during routing, users can easily return to Capture wiring diagram, and update the wiring diagram to Allegro after modification.
Users can also click and modify objects between Capture and Allegro.
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