vivado联合modelsim仿真，modelsim无法正常弹出求助

前天发布

刚拿到师兄的工程，他用vivado自带的仿真的时候会有正常的波形，而且代码已经上过板子了，不会有问题。但是我用modelsim仿真的时候modelsim根本弹不出来，会一直加载，无奈只能手动取消。这个工程里面有一个模块是用simulink生成的，里面的.v文件特别多，当不加这个模块进行仿真的时候，modelsim可以正常运行，但是加了之后就不行了。报错信息说是file name too long 我尝试把这个工程放到根目录了，还是报这个错误，所以我怀疑是.v文件太多导致的，但是这个模块又不能改。希望大家帮我分析分析到底是不是我猜的这个原因，如果是的话怎么解决，如果不是，怎么排查。vivado tcl console里面完整的信息放到下面了，报错的内容我进行了加粗。希望有好心的大佬帮帮忙

launch_simulation -install_path E:/EDATOOLS/Modelsim/win64 -gcc_install_path E:/EDATOOLS/sim_lib_2020_2
Command: launch_simulation -install_path E:/EDATOOLS/Modelsim/win64 -gcc_install_path E:/EDATOOLS/sim_lib_2020_2
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the ‘ModelSim’ simulator…
INFO: [Vivado 12-5682] Launching behavioral simulation in ‘E:/ETH_TX_ps_qam/ETH_TX.sim/sim_1/behav/modelsim’
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [USF-ModelSim-47] Finding simulator installation…
INFO: [USF-ModelSim-50] Using simulator executables from ‘E:/EDATOOLS/Modelsim/win64/vsim.exe’
INFO: [SIM-utils-51] Simulation object is ‘sim_1’
INFO: [USF-modelsim-7] Finding pre-compiled libraries…
INFO: [USF-modelsim-11] File ‘E:/EDATOOLS/sim_lib_2020_2/modelsim.ini’ copied to run dir:’E:/ETH_TX_ps_qam/ETH_TX.sim/sim_1/behav/modelsim’
INFO: [SIM-utils-54] Inspecting design source files for ‘sim_TX_DA_TOP’ in fileset ‘sim_1’…
INFO: [SIM-utils-43] Exported ‘E:/ETH_TX_ps_qam/ETH_TX.sim/sim_1/behav/modelsim/blk_mem_train_im.mif’
INFO: [SIM-utils-43] Exported ‘E:/ETH_TX_ps_qam/ETH_TX.sim/sim_1/behav/modelsim/zc512_im0_div8.coe’
INFO: [SIM-utils-43] Exported ‘E:/ETH_TX_ps_qam/ETH_TX.sim/sim_1/behav/modelsim/blk_mem_train_re.mif’
INFO: [SIM-utils-43] Exported ‘E:/ETH_TX_ps_qam/ETH_TX.sim/sim_1/behav/modelsim/zc512_re0_div8.coe’
INFO: [SIM-utils-43] Exported ‘E:/ETH_TX_ps_qam/ETH_TX.sim/sim_1/behav/modelsim/init_rom_2594.mif’
INFO: [SIM-utils-43] Exported ‘E:/ETH_TX_ps_qam/ETH_TX.sim/sim_1/behav/modelsim/lmx2594_config.coe’
INFO: [SIM-utils-43] Exported ‘E:/ETH_TX_ps_qam/ETH_TX.sim/sim_1/behav/modelsim/init_rom_adc.mif’
INFO: [SIM-utils-43] Exported ‘E:/ETH_TX_ps_qam/ETH_TX.sim/sim_1/behav/modelsim/dac_config_single6G4.coe’
INFO: [SIM-utils-43] Exported ‘E:/ETH_TX_ps_qam/ETH_TX.sim/sim_1/behav/modelsim/init_rom_pll.mif’
INFO: [SIM-utils-43] Exported ‘E:/ETH_TX_ps_qam/ETH_TX.sim/sim_1/behav/modelsim/hmc7044_config.coe’
INFO: [SIM-utils-43] Exported ‘E:/ETH_TX_ps_qam/ETH_TX.sim/sim_1/behav/modelsim/rom_im.mif’
INFO: [SIM-utils-43] Exported ‘E:/ETH_TX_ps_qam/ETH_TX.sim/sim_1/behav/modelsim/time_head_im.coe’
INFO: [SIM-utils-43] Exported ‘E:/ETH_TX_ps_qam/ETH_TX.sim/sim_1/behav/modelsim/rom_re.mif’
INFO: [SIM-utils-43] Exported ‘E:/ETH_TX_ps_qam/ETH_TX.sim/sim_1/behav/modelsim/time_head_re.coe’
INFO: [SIM-utils-43] Exported ‘E:/ETH_TX_ps_qam/ETH_TX.sim/sim_1/behav/modelsim/re_head_re_32_16.coe’
INFO: [SIM-utils-43] Exported ‘E:/ETH_TX_ps_qam/ETH_TX.sim/sim_1/behav/modelsim/re_head_im_32_16.coe’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/blk_mem_train_im/blk_mem_train_im.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/blk_mem_train_re/blk_mem_train_re.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/clk_wiz_DA/clk_wiz_DA.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/clk_wiz_PHY/clk_wiz_PHY.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/fifo_192/fifo_192.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/fifo_256/fifo_256.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/fifo_generator_2/fifo_generator_2.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/fifo_train_combine/fifo_train_combine.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/ila_0/ila_0.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/ila_combine/ila_combine.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/ila_compensation/ila_compensation.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/ila_cp/ila_cp.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/ila_data_cut/ila_data_cut.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/ila_data_gen/ila_data_gen.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/ila_preamble_out/ila_preamble_out.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/ila_qam/ila_qam.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/ila_reshape_scram/ila_reshape_scram.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/ila_rs/ila_rs.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/ila_scram/ila_scram.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/ila_train_combine/ila_train_combine.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/init_rom_2594/init_rom_2594.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/init_rom_adc/init_rom_adc.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/init_rom_pll/init_rom_pll.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/jesd204_tx/jesd204_tx.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/jesd204_tx_phy/jesd204_tx_phy.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/jesd204_tx_phy_1/jesd204_tx_phy_1.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/mult_gen/mult_gen.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/shift_ram/shift_ram.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/vio_data_gen/vio_data_gen.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/vio_multi/vio_multi.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/vio_reset/vio_reset.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/jesd204_tx_phy_1/ip_0/jesd204_tx_phy_1_gt.xml’
WARNING: [SIM-utils-52] IP component XML file does not exist: ‘e:/ETH_TX_ps_qam/ETH_TX.srcs/sources_1/ip/jesd204_tx_phy/ip_0/jesd204_tx_phy_gt.xml’
INFO: [USF-ModelSim-107] Finding global include files…
INFO: [USF-ModelSim-108] Finding include directories and verilog header directory paths…
INFO: [USF-ModelSim-109] Fetching design files from ‘sim_1’…
INFO: [USF-ModelSim-2] ModelSim::Compile design
INFO: [USF-ModelSim-15] Creating automatic ‘do’ files…
INFO: [USF-ModelSim-69] Executing ‘COMPILE and ANALYZE’ step in ‘E:/ETH_TX_ps_qam/ETH_TX.sim/sim_1/behav/modelsim’
Reading E:/EDATOOLS/Modelsim/tcl/vsim/pref.tcl

# 10.7

# do {sim_TX_DA_TOP_compile.do}
# ** Warning: (vlib-34) Library already exists at “modelsim_lib/work”.
# ** Warning: (vlib-34) Library already exists at “modelsim_lib/msim”.
# ** Warning: (vlib-34) Library already exists at “modelsim_lib/msim/xil_defaultlib”.
# Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017
# vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
# Modifying modelsim.ini
# Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017
# Start time: 09:33:15 on May 19,2025
# vlog -incr -work xil_defaultlib “+incdir+../../../../ETH_TX.gen/sources_1/ip/clk_wiz_0” “+incdir+../../../../ETH_TX.srcs/sources_1/ip/clk_wiz_DA” “+incdir+../../../../ETH_TX.srcs/sources_1/ip/clk_wiz_PHY” “+incdir+E:/EDATOOLS/vivado2020_2/Vivado/2020.2/data/xilinx_vip/include” ../../../../ETH_TX.ip_user_files/ip/ila_data_cut/sim/ila_data_cut.v ../../../../ETH_TX.ip_user_files/ip/ila_data_gen/sim/ila_data_gen.v ../../../../ETH_TX.ip_user_files/ip/vio_data_gen/sim/vio_data_gen.v ../../../../ETH_TX.ip_user_files/ip/ila_preamble_out/sim/ila_preamble_out.v ../../../../ETH_TX.ip_user_files/ip/fifo_generator_2/sim/fifo_generator_2.v ../../../../ETH_TX.gen/sources_1/ip/rom_im/sim/rom_im.v ../../../../ETH_TX.gen/sources_1/ip/rom_re/sim/rom_re.v ../../../../ETH_TX.ip_user_files/ip/ila_cp/sim/ila_cp.v ../../../../ETH_TX.gen/sources_1/ip/fifo_generator_0/sim/fifo_generator_0.v ../../../../ETH_TX.ip_user_files/ip/ila_0/sim/ila_0.v
# — Skipping module ila_data_cut
# — Skipping module ila_data_gen
# — Skipping module vio_data_gen
# — Skipping module ila_preamble_out
# — Skipping module fifo_generator_2
# — Skipping module rom_im
# — Skipping module rom_re
# — Skipping module ila_cp
# — Skipping module fifo_generator_0
# — Skipping module ila_0
#
# Top level modules:
# ila_data_cut
# ila_data_gen
# vio_data_gen
# ila_preamble_out
# fifo_generator_2
# rom_im
# rom_re
# ila_cp
# fifo_generator_0
# ila_0
# End time: 09:33:15 on May 19,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017
# Start time: 09:33:15 on May 19,2025
# vcom -93 -work xil_defaultlib ../../../../ETH_TX.ip_user_files/ip/mult_gen/sim/mult_gen.vhd
# — Loading package STANDARD
# — Loading package TEXTIO
# — Loading package std_logic_1164
# — Loading package NUMERIC_STD
# — Compiling entity mult_gen
# — Compiling architecture mult_gen_arch of mult_gen
# End time: 09:33:15 on May 19,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017
# Start time: 09:33:15 on May 19,2025
# vlog -incr -work xil_defaultlib “+incdir+../../../../ETH_TX.gen/sources_1/ip/clk_wiz_0” “+incdir+../../../../ETH_TX.srcs/sources_1/ip/clk_wiz_DA” “+incdir+../../../../ETH_TX.srcs/sources_1/ip/clk_wiz_PHY” “+incdir+E:/EDATOOLS/vivado2020_2/Vivado/2020.2/data/xilinx_vip/include” ../../../../ETH_TX.ip_user_files/ip/ila_compensation/sim/ila_compensation.v ../../../../ETH_TX.ip_user_files/ip/vio_multi/sim/vio_multi.v ../../../../ETH_TX.ip_user_files/ip/ila_train_combine/sim/ila_train_combine.v ../../../../ETH_TX.ip_user_files/ip/fifo_train_combine/sim/fifo_train_combine.v
# — Skipping module ila_compensation
# — Skipping module vio_multi
# — Skipping module ila_train_combine
# — Skipping module fifo_train_combine
#
# Top level modules:
# ila_compensation
# vio_multi
# ila_train_combine
# fifo_train_combine
# End time: 09:33:15 on May 19,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017
# Start time: 09:33:16 on May 19,2025
# vcom -93 -work xil_defaultlib ../../../../ETH_TX.ip_user_files/ip/shift_ram/sim/shift_ram.vhd
# — Loading package STANDARD
# — Loading package TEXTIO
# — Loading package std_logic_1164
# — Loading package NUMERIC_STD
# — Compiling entity shift_ram
# — Compiling architecture shift_ram_arch of shift_ram
# End time: 09:33:16 on May 19,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017
# Start time: 09:33:17 on May 19,2025
# vlog -incr -work xil_defaultlib “+incdir+../../../../ETH_TX.gen/sources_1/ip/clk_wiz_0” “+incdir+../../../../ETH_TX.srcs/sources_1/ip/clk_wiz_DA” “+incdir+../../../../ETH_TX.srcs/sources_1/ip/clk_wiz_PHY” “+incdir+E:/EDATOOLS/vivado2020_2/Vivado/2020.2/data/xilinx_vip/include” ../../../../ETH_TX.ip_user_files/ip/blk_mem_train_im/sim/blk_mem_train_im.v ../../../../ETH_TX.ip_user_files/ip/blk_mem_train_re/sim/blk_mem_train_re.v
# — Skipping module blk_mem_train_im
# — Skipping module blk_mem_train_re
#
# Top level modules:
# blk_mem_train_im
# blk_mem_train_re
# End time: 09:33:17 on May 19,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017
# Start time: 09:33:17 on May 19,2025
# vcom -93 -work xil_defaultlib ../../../../ETH_TX.gen/sources_1/ip/rs_encoder_0/sim/rs_encoder_0.vhd
# — Loading package STANDARD
# — Loading package TEXTIO
# — Loading package std_logic_1164
# — Loading package NUMERIC_STD
# — Compiling entity rs_encoder_0
# — Compiling architecture rs_encoder_0_arch of rs_encoder_0
# End time: 09:33:17 on May 19,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# ** Error: couldn’t execute “E:\EDATOOLS\Modelsim\win64\vlog.EXE”: file name too long
# Error in macro ./sim_TX_DA_TOP_compile.do line 1264
# couldn’t execute “E:\EDATOOLS\Modelsim\win64\vlog.EXE”: file name too long
# while executing
# “exec <nul: {E:\EDATOOLS\Modelsim\win64\vlog.EXE} -incr -work xil_defaultlib +incdir+../../../../ETH_TX.gen/sources_1/ip/clk_wiz_0 +incdir+../../../../…”
# (“uplevel” body line 1)
# invoked from within
# “uplevel 1 exec $redir $new [lrange $args 1 end]”
# (procedure “::unknown” line 47)
# invoked from within
# “E:\\EDATOOLS\\Modelsim\\win64\\vlog -incr -work xil_defaultlib “+incdir+../../../../ETH_TX.gen/sources_1/ip/clk_wiz_0” “+incdir+../../../../ETH_TX.s…”
ModelSim> INFO: [Common 17-41] Interrupt caught. Command should exit soon.
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:22 . Memory (MB): peak = 1627.855 ; gain = 0.000
INFO: [Common 17-344] ‘run_program’ was cancelled
INFO: [Vivado 12-5357] ‘compile’ step aborted
launch_simulation: Time (s): cpu = 00:00:11 ; elapsed = 00:00:38 . Memory (MB): peak = 1627.855 ; gain = 7.812
INFO: [Common 17-344] ‘launch_simulation’ was cancelled

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