/** * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * 2. Redistributions in binary form, except as embedded into a Nordic * Semiconductor ASA integrated circuit in a product or a software update for * such product, must reproduce the above copyright notice, this list of * conditions and the following disclaimer in the documentation and/or other * materials provided with the distribution. * * 3. Neither the name of Nordic Semiconductor ASA nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * 4. This software, with or without modification, must only be used with a * Nordic Semiconductor ASA integrated circuit. * * 5. Any software provided in binary form under this license must not be reverse * engineered, decompiled, modified and/or disassembled. * * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ #ifndef NRF_GPIO_H__ #define NRF_GPIO_H__ #include <nrfx.h> #ifdef __cplusplus extern "C" { #endif #ifndef NRF_P0 #define NRF_P0 NRF_GPIO #endif #if (GPIO_COUNT == 1) #define NUMBER_OF_PINS (P0_PIN_NUM) #define GPIO_REG_LIST {NRF_P0} #elif (GPIO_COUNT == 2) #define NUMBER_OF_PINS (P0_PIN_NUM + P1_PIN_NUM) #define GPIO_REG_LIST {NRF_P0, NRF_P1} #else #error "Not supported." #endif #if defined(NRF52820_XXAA) #include <nrf_erratas.h> #endif /** * @defgroup nrf_gpio_hal GPIO HAL * @{ * @ingroup nrf_gpio * @brief Hardware access layer for managing the GPIO peripheral. */ #if defined(GPIO_LATCH_PIN0_Msk) || defined(__NRFX_DOXYGEN__) /** @brief Symbol indicating whether the functionality of latching GPIO state change is present. */ #define NRF_GPIO_LATCH_PRESENT #endif /** @brief Macro for mapping port and pin numbers to values understandable for nrf_gpio functions. */ #define NRF_GPIO_PIN_MAP(port, pin) (((port) << 5) | ((pin) & 0x1F)) /** @brief Pin direction definitions. */ typedef enum { NRF_GPIO_PIN_DIR_INPUT = GPIO_PIN_CNF_DIR_Input, ///< Input. NRF_GPIO_PIN_DIR_OUTPUT = GPIO_PIN_CNF_DIR_Output ///< Output. } nrf_gpio_pin_dir_t; /** @brief Connection of input buffer. */ typedef enum { NRF_GPIO_PIN_INPUT_CONNECT = GPIO_PIN_CNF_INPUT_Connect, ///< Connect input buffer. NRF_GPIO_PIN_INPUT_DISCONNECT = GPIO_PIN_CNF_INPUT_Disconnect ///< Disconnect input buffer. } nrf_gpio_pin_input_t; /** * @brief Enumerator used for selecting the pin to be pulled down or up at the time of pin * configuration. */ typedef enum { NRF_GPIO_PIN_NOPULL = GPIO_PIN_CNF_PULL_Disabled, ///< Pin pull-up resistor disabled. NRF_GPIO_PIN_PULLDOWN = GPIO_PIN_CNF_PULL_Pulldown, ///< Pin pull-down resistor enabled. NRF_GPIO_PIN_PULLUP = GPIO_PIN_CNF_PULL_Pullup, ///< Pin pull-up resistor enabled. } nrf_gpio_pin_pull_t; /** @brief Enumerator used for selecting output drive mode. */ typedef enum { NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< !< Standard '0', standard '1'. NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< !< High-drive '0', standard '1'. NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< !< Standard '0', high-drive '1'. NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE_H0H1, ///< !< High drive '0', high-drive '1'. NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE_D0S1, ///< !< Disconnect '0' standard '1'. NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE_D0H1, ///< !< Disconnect '0', high-drive '1'. NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE_S0D1, ///< !< Standard '0', disconnect '1'. NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< !< High-drive '0', disconnect '1'. } nrf_gpio_pin_drive_t; /** @brief Enumerator used for selecting the pin to sense high or low level on the pin input. */ typedef enum { NRF_GPIO_PIN_NOSENSE = GPIO_PIN_CNF_SENSE_Disabled, ///< Pin sense level disabled. NRF_GPIO_PIN_SENSE_LOW = GPIO_PIN_CNF_SENSE_Low, ///< Pin sense low level. NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High, ///< Pin sense high level. } nrf_gpio_pin_sense_t; /** * @brief Function for configuring the GPIO pin range as output pins with normal drive strength. * This function can be used to configure pin range as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases). * * @note For configuring only one pin as output, use @ref nrf_gpio_cfg_output. * Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output. * * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). */ __STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end); /** * @brief Function for configuring the GPIO pin range as input pins with given initial value set, hiding inner details. * This function can be used to configure pin range as simple input. * * @note For configuring only one pin as input, use @ref nrf_gpio_cfg_input. * Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable. * * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high). */ __STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, uint32_t pin_range_end, nrf_gpio_pin_pull_t pull_config); /** * @brief Pin configuration function. * * The main pin configuration function. * This function allows to set any aspect in PIN_CNF register. * * @param pin_number Specifies the pin number. * @param dir Pin direction. * @param input Connect or disconnect the input buffer. * @param pull Pull configuration. * @param drive Drive configuration. * @param sense Pin sensing mechanism. */ __STATIC_INLINE void nrf_gpio_cfg( uint32_t pin_number, nrf_gpio_pin_dir_t dir, nrf_gpio_pin_input_t input, nrf_gpio_pin_pull_t pull, nrf_gpio_pin_drive_t drive, nrf_gpio_pin_sense_t sense); /** * @brief Function for configuring the given GPIO pin number as output, hiding inner details. * This function can be used to configure a pin as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases). * * @note Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output. * * @param pin_number Specifies the pin number. */ __STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number); /** * @brief Function for configuring the given GPIO pin number as input, hiding inner details. * This function can be used to configure a pin as simple input. * * @note Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable. * * @param pin_number Specifies the pin number. * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high). */ __STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config); /** * @brief Function for resetting pin configuration to its default state. * * @param pin_number Specifies the pin number. */ __STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number); /** * @brief Function for configuring the given GPIO pin number as a watcher. Only input is connected. * * @param pin_number Specifies the pin number. * */ __STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number); /** * @brief Function for disconnecting input for the given GPIO. * * @param pin_number Specifies the pin number. */ __STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number); /** * @brief Function for configuring the given GPIO pin number as input, hiding inner details. * This function can be used to configure pin range as simple input. * Sense capability on the pin is configurable and input is connected to buffer so that the GPIO->IN register is readable. * * @param pin_number Specifies the pin number. * @param pull_config State of the pin pull resistor (no pull, pulled down, or pulled high). * @param sense_config Sense level of the pin (no sense, sense low, or sense high). */ __STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config, nrf_gpio_pin_sense_t sense_config); /** * @brief Function for configuring sense level for the given GPIO. * * @param pin_number Specifies the pin number. * @param sense_config Sense configuration. */ __STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config); /** * @brief Function for setting the direction for a GPIO pin. * * @param pin_number Specifies the pin number for which to set the direction. * @param direction Specifies the direction. */ __STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction); /** * @brief Function for setting a GPIO pin. * * For this function to have any effect, the pin must be configured as an output. * * @param pin_number Specifies the pin number to be set. */ __STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number); /** * @brief Function for clearing a GPIO pin. * * For this function to have any effect, the pin must be configured as an output. * * @param pin_number Specifies the pin number to clear. */ __STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number); /** * @brief Function for toggling a GPIO pin. * * For this function to have any effect, the pin must be configured as an output. * * @param pin_number Specifies the pin number to toggle. */ __STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number); /** * @brief Function for writing a value to a GPIO pin. * * For this function to have any effect, the pin must be configured as an output. * * @param pin_number Specifies the pin number to write. * @param value Specifies the value to be written to the pin. * @arg 0 Clears the pin. * @arg >=1 Sets the pin. */ __STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value); /** * @brief Function for reading the input level of a GPIO pin. * * If the value returned by this function is to be valid, the pin's input buffer must be connected. * * @param pin_number Specifies the pin number to read. * * @return 0 if the pin input level is low. Positive value if the pin is high. */ __STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number); /** * @brief Function for reading the output level of a GPIO pin. * * @param pin_number Specifies the pin number to read. * * @return 0 if the pin output level is low. Positive value if pin output is high. */ __STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number); /** * @brief Function for reading the sense configuration of a GPIO pin. * * @param pin_number Specifies the pin number to read. * * @return Sense configuration. */ __STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number); /** * @brief Function for reading the direction configuration of a GPIO pin. * * @param pin_number Specifies the pin number to read. * * @return Direction configuration. */ __STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number); /** * @brief Function for reading the status of GPIO pin input buffer. * * @param pin_number Pin number to be read. * * @retval Input buffer configuration. */ __STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number); /** * @brief Function for reading the pull configuration of a GPIO pin. * * @param pin_number Specifies the pin number to read. * * @retval Pull configuration. */ __STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number); /** * @brief Function for setting output direction on the selected pins on the given port. * * @param p_reg Pointer to the structure of registers of the peripheral. * @param out_mask Mask specifying the pins to set as output. */ __STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask); /** * @brief Function for setting input direction on selected pins on a given port. * * @param p_reg Pointer to the structure of registers of the peripheral. * @param in_mask Mask that specifies the pins to be set as input. */ __STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask); /** * @brief Function for writing the direction configuration of the GPIO pins in the given port. * * @param p_reg Pointer to the structure of registers of the peripheral. * @param dir_mask Mask that specifies the direction of pins. Bit set means that the given pin is configured as output. */ __STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t dir_mask); /** * @brief Function for reading the direction configuration of a GPIO port. * * @param p_reg Pointer to the structure of registers of the peripheral. * * @return Pin configuration of the current direction settings. Bit set means that the given pin is configured as output. */ __STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg); /** * @brief Function for reading the input signals of the GPIO pins on the given port. * * @param p_reg Pointer to the peripheral registers structure. * * @return Port input values. */ __STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg); /** * @brief Function for reading the output signals of the GPIO pins on the given port. * * @param p_reg Pointer to the peripheral registers structure. * * @return Port output values. */ __STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg); /** * @brief Function for writing the GPIO pins output on a given port. * * @param p_reg Pointer to the structure of registers of the peripheral. * @param value Output port mask. */ __STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value); /** * @brief Function for setting high level on selected the GPIO pins on the given port. * * @param p_reg Pointer to the structure of registers of the peripheral. * @param set_mask Mask with pins to be set as logical high level. */ __STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask); /** * @brief Function for setting low level on selected the GPIO pins on the given port. * * @param p_reg Pointer to the structure of registers of the peripheral. * @param clr_mask Mask with pins to be set as logical low level. */ __STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask); /** * @brief Function for reading pin state of multiple consecutive ports. * * @param start_port Index of the first port to read. * @param length Number of ports to read. * @param p_masks Pointer to output array where port states will be stored. */ __STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, uint32_t length, uint32_t * p_masks); #if defined(NRF_GPIO_LATCH_PRESENT) /** * @brief Function for reading latch state of multiple consecutive ports. * * @param start_port Index of the first port to read. * @param length Number of ports to read. * @param p_masks Pointer to output array where latch states will be stored. */ __STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, uint32_t length, uint32_t * p_masks); /** * @brief Function for reading and immediate clearing latch state of multiple consecutive ports. * * @param start_port Index of the first port to read and clear. * @param length Number of ports to read and clear. * @param p_masks Pointer to output array where latch states will be stored. */ __STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port, uint32_t length, uint32_t * p_masks); /** * @brief Function for reading latch state of single pin. * * @param pin_number Pin number. * * @return 0 if latch is not set. Positive value otherwise. */ __STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number); /** * @brief Function for clearing latch state of a single pin. * * @param pin_number Pin number. */ __STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number); #endif // defined(NRF_GPIO_LATCH_PRESENT) /** * @brief Function for checking if provided pin is present on the MCU. * * @param[in] pin_number Number of the pin to be checked. * * @retval true Pin is present. * @retval false Pin is not present. */ __STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number); #ifndef SUPPRESS_INLINE_IMPLEMENTATION /** * @brief Function for extracting port and the relative pin number from the absolute pin number. * * @param[in,out] p_pin Pointer to the absolute pin number overriden by the pin number that is relative to the port. * * @return Pointer to port register set. */ __STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin) { NRFX_ASSERT(nrf_gpio_pin_present_check(*p_pin)); #if (GPIO_COUNT == 1) return NRF_P0; #else if (*p_pin < P0_PIN_NUM) { return NRF_P0; } else { *p_pin = *p_pin & 0x1F; return NRF_P1; } #endif } __STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end) { /*lint -e{845} // A zero has been given as right argument to operator '|'" */ for (; pin_range_start <= pin_range_end; pin_range_start++) { nrf_gpio_cfg_output(pin_range_start); } } __STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, uint32_t pin_range_end, nrf_gpio_pin_pull_t pull_config) { /*lint -e{845} // A zero has been given as right argument to operator '|'" */ for (; pin_range_start <= pin_range_end; pin_range_start++) { nrf_gpio_cfg_input(pin_range_start, pull_config); } } __STATIC_INLINE void nrf_gpio_cfg( uint32_t pin_number, nrf_gpio_pin_dir_t dir, nrf_gpio_pin_input_t input, nrf_gpio_pin_pull_t pull, nrf_gpio_pin_drive_t drive, nrf_gpio_pin_sense_t sense) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos) | ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) | ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos) | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) | ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos); } __STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number) { nrf_gpio_cfg( pin_number, NRF_GPIO_PIN_DIR_OUTPUT, NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); } __STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config) { nrf_gpio_cfg( pin_number, NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, pull_config, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); } __STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number) { nrf_gpio_cfg( pin_number, NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); } __STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); /*lint -e{845} // A zero has been given as right argument to operator '|'" */ uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk; reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos); } __STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); /*lint -e{845} // A zero has been given as right argument to operator '|'" */ uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk; reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos); } __STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config, nrf_gpio_pin_sense_t sense_config) { nrf_gpio_cfg( pin_number, NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, pull_config, NRF_GPIO_PIN_S0S1, sense_config); } __STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); /*lint -e{845} // A zero has been given as right argument to operator '|'" */ reg->PIN_CNF[pin_number] &= ~GPIO_PIN_CNF_SENSE_Msk; reg->PIN_CNF[pin_number] |= (sense_config << GPIO_PIN_CNF_SENSE_Pos); } __STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction) { if (direction == NRF_GPIO_PIN_DIR_INPUT) { nrf_gpio_cfg( pin_number, NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); } else { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); reg->DIRSET = (1UL << pin_number); } } __STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); nrf_gpio_port_out_set(reg, 1UL << pin_number); } __STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); nrf_gpio_port_out_clear(reg, 1UL << pin_number); } __STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); uint32_t pins_state = reg->OUT; reg->OUTSET = (~pins_state & (1UL << pin_number)); reg->OUTCLR = (pins_state & (1UL << pin_number)); } __STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value) { if (value == 0) { nrf_gpio_pin_clear(pin_number); } else { nrf_gpio_pin_set(pin_number); } } __STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL); } __STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); return ((nrf_gpio_port_out_read(reg) >> pin_number) & 1UL); } __STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos); } __STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_DIR_Msk) >> GPIO_PIN_CNF_DIR_Pos); } __STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); return (nrf_gpio_pin_input_t)((reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_INPUT_Msk) >> GPIO_PIN_CNF_INPUT_Pos); } __STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); return (nrf_gpio_pin_pull_t)((reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_PULL_Msk) >> GPIO_PIN_CNF_PULL_Pos); } __STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask) { p_reg->DIRSET = out_mask; } __STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask) { p_reg->DIRCLR = in_mask; } __STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t value) { p_reg->DIR = value; } __STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg) { return p_reg->DIR; } __STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg) { return p_reg->IN; } __STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg) { return p_reg->OUT; } __STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value) { p_reg->OUT = value; } __STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask) { p_reg->OUTSET = set_mask; } __STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask) { p_reg->OUTCLR = clr_mask; } __STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, uint32_t length, uint32_t * p_masks) { NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST; NRFX_ASSERT(start_port + length <= GPIO_COUNT); uint32_t i; for (i = start_port; i < (start_port + length); i++) { *p_masks = nrf_gpio_port_in_read(gpio_regs[i]); p_masks++; } } #if defined(NRF_GPIO_LATCH_PRESENT) __STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, uint32_t length, uint32_t * p_masks) { NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST; uint32_t i; for (i = start_port; i < (start_port + length); i++) { *p_masks = gpio_regs[i]->LATCH; p_masks++; } } __STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port, uint32_t length, uint32_t * p_masks) { NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST; uint32_t i; for (i = start_port; i < (start_port + length); i++) { *p_masks = gpio_regs[i]->LATCH; // The LATCH register is cleared by writing a '1' to the bit that shall be cleared. gpio_regs[i]->LATCH = *p_masks; p_masks++; } } __STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); return (reg->LATCH & (1 << pin_number)) ? 1 : 0; } __STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); reg->LATCH = (1 << pin_number); } #endif // defined(NRF_GPIO_LATCH_PRESENT) __STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number) { uint32_t port = pin_number >> 5; uint32_t mask = 0; switch (port) { #ifdef P0_FEATURE_PINS_PRESENT case 0: mask = P0_FEATURE_PINS_PRESENT; #if defined(NRF52820_XXAA) && defined(DEVELOP_IN_NRF52833) /* Allow use of the following additional GPIOs that are connected to LEDs and buttons * on the nRF52833 DK: * - P0.11 - Button 1 * - P0.12 - Button 2 * - P0.13 - LED 1 * - P0.24 - Button 3 * - P0.25 - Button 4 */ mask |= 0x03003800; #endif // defined(NRF52820_XXAA) && defined(DEVELOP_IN_NRF52833) break; #endif #ifdef P1_FEATURE_PINS_PRESENT case 1: mask = P1_FEATURE_PINS_PRESENT; break; #endif } pin_number &= 0x1F; return (mask & (1UL << pin_number)) ? true : false; } #endif // SUPPRESS_INLINE_IMPLEMENTATION /** @} */ #ifdef __cplusplus } #endif #endif // NRF_GPIO_H__ 代码学习：
Nordic Semiconductor GPIO 硬件抽象层代码解析
整体结构与功能概述
这段代码是 Nordic Semiconductor 为 nRF52 系列芯片设计的 GPIO 硬件抽象层（HAL），提供了对通用输入输出端口的配置和操作接口。代码主要包含以下几个部分：
- 版权与许可声明
- 头文件保护与条件编译
- GPIO 配置相关的枚举类型定义
- GPIO 操作函数声明（内联函数）
- 函数的内联实现
- C++ 兼容性处理
版权与许可部分
/** * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * ...（中间是许可条件，共5条）... * * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. * ...（省略责任声明）... */ 这部分是 Nordic Semiconductor 的版权声明和许可协议，规定了代码的使用、修改和分发条件。
头文件保护与条件编译
#ifndef NRF_GPIO_H__ #define NRF_GPIO_H__ #include <nrfx.h> #ifdef __cplusplus extern "C" { #endif #ifndef NRF_P0 #define NRF_P0 NRF_GPIO #endif #if (GPIO_COUNT == 1) #define NUMBER_OF_PINS (P0_PIN_NUM) #define GPIO_REG_LIST {NRF_P0} #elif (GPIO_COUNT == 2) #define NUMBER_OF_PINS (P0_PIN_NUM + P1_PIN_NUM) #define GPIO_REG_LIST {NRF_P0, NRF_P1} #else #error "Not supported." #endif #if defined(NRF52820_XXAA) #include <nrf_erratas.h> #endif - 头文件保护：使用
#ifndef NRF_GPIO_H__防止头文件重复包含 - C++ 兼容性：通过
extern "C"确保 C++ 环境中函数声明的兼容性 - GPIO 端口定义：根据
GPIO_COUNT宏定义确定支持的 GPIO 端口数量（1 个或 2 个） - 芯片特定包含：针对 NRF52820 芯片包含错误修正头文件
枚举类型定义
代码定义了多个枚举类型，用于配置 GPIO 引脚的各种属性：
/** @brief Pin direction definitions. */ typedef enum { NRF_GPIO_PIN_DIR_INPUT = GPIO_PIN_CNF_DIR_Input, ///< 输入模式 NRF_GPIO_PIN_DIR_OUTPUT = GPIO_PIN_CNF_DIR_Output ///< 输出模式 } nrf_gpio_pin_dir_t; /** @brief Connection of input buffer. */ typedef enum { NRF_GPIO_PIN_INPUT_CONNECT = GPIO_PIN_CNF_INPUT_Connect, ///< 连接输入缓冲 NRF_GPIO_PIN_INPUT_DISCONNECT = GPIO_PIN_CNF_INPUT_Disconnect ///< 断开输入缓冲 } nrf_gpio_pin_input_t; /** @brief 引脚上下拉配置枚举 */ typedef enum { NRF_GPIO_PIN_NOPULL = GPIO_PIN_CNF_PULL_Disabled, ///< 无上下拉 NRF_GPIO_PIN_PULLDOWN = GPIO_PIN_CNF_PULL_Pulldown, ///< 下拉电阻 NRF_GPIO_PIN_PULLUP = GPIO_PIN_CNF_PULL_Pullup, ///< 上拉电阻 } nrf_gpio_pin_pull_t; 这些枚举类型将 GPIO 寄存器的配置值映射为有意义的符号名称，便于开发者使用。每个枚举值都对应到芯片寄存器的具体位配置（如 GPIO_PIN_CNF_DIR_Input 对应输入方向配置）。
GPIO 操作函数声明
代码中声明了大量内联函数，用于配置和操作 GPIO 引脚：
/** * @brief 配置GPIO引脚范围为输出模式 * @param pin_range_start 起始引脚号 * @param pin_range_end 结束引脚号 */ __STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end); /** * @brief 配置GPIO引脚范围为输入模式 * @param pin_range_start 起始引脚号 * @param pin_range_end 结束引脚号 * @param pull_config 上下拉配置 */ __STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, uint32_t pin_range_end, nrf_gpio_pin_pull_t pull_config); /** * @brief 完整的引脚配置函数 * @param pin_number 引脚号 * @param dir 方向配置 * @param input 输入缓冲连接状态 * @param pull 上下拉配置 * @param drive 驱动能力配置 * @param sense 感应配置 */ __STATIC_INLINE void nrf_gpio_cfg( uint32_t pin_number, nrf_gpio_pin_dir_t dir, nrf_gpio_pin_input_t input, nrf_gpio_pin_pull_t pull, nrf_gpio_pin_drive_t drive, nrf_gpio_pin_sense_t sense); 这些函数提供了从简单到复杂的各种 GPIO 配置接口，包括：
- 单引脚配置与批量引脚配置
- 输入输出模式设置
- 上下拉电阻配置
- 驱动能力设置
- 电平感应功能配置
内联函数实现
内联函数实现了具体的寄存器操作：
__STATIC_INLINE void nrf_gpio_cfg( uint32_t pin_number, nrf_gpio_pin_dir_t dir, nrf_gpio_pin_input_t input, nrf_gpio_pin_pull_t pull, nrf_gpio_pin_drive_t drive, nrf_gpio_pin_sense_t sense) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos) | ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) | ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos) | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) | ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos); } 这个核心配置函数通过位运算将各个配置参数组合成一个完整的寄存器值，写入 PIN_CNF 寄存器。每个配置参数通过左移操作定位到寄存器的对应位位置，然后通过按位或操作组合成最终的配置值。
引脚操作函数
/** * @brief 设置GPIO引脚为高电平 * @param pin_number 引脚号 */ __STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); nrf_gpio_port_out_set(reg, 1UL << pin_number); } /** * @brief 清除GPIO引脚为低电平 * @param pin_number 引脚号 */ __STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); nrf_gpio_port_out_clear(reg, 1UL << pin_number); } /** * @brief 翻转GPIO引脚电平 * @param pin_number 引脚号 */ __STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); uint32_t pins_state = reg->OUT; reg->OUTSET = (~pins_state & (1UL << pin_number)); reg->OUTCLR = (pins_state & (1UL << pin_number)); } 这些函数实现了对 GPIO 引脚的基本操作：设置高电平、清除低电平、翻转电平。通过操作 OUTSET 和 OUTCLR 寄存器，确保了对引脚输出的原子操作。
其中nrf_gpio_pin_toggle函数解析如下：
这段代码实现了 nRF 系列微控制器 GPIO 引脚状态切换功能。下面是对该函数的详细解释：
- 函数原型
__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number); __STATIC_INLINE：GCC 编译器特定的静态内联函数声明pin_number：要切换的 GPIO 引脚编号
- 寄存器操作原理
NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); uint32_t pins_state = reg->OUT; - 通过
nrf_gpio_pin_port_decode获取引脚对应的 GPIO 端口寄存器基址 - 读取当前整个端口的输出状态
- 翻转逻辑实现
reg->OUTSET = (~pins_state & (1UL << pin_number)); reg->OUTCLR = (pins_state & (1UL << pin_number)); OUTSET寄存器：设置为 1 的位会将对应引脚置高OUTCLR寄存器：设置为 1 的位会将对应引脚置低- 通过位运算实现只翻转目标引脚而不影响其他引脚
- 执行效果示例
假设：
- 当前
OUT寄存器值为0b00001000(第 3 位为 1) - 要翻转第 1 位 (pin_number=1)
执行过程：
1UL << 1 = 0b00000010 ~pins_state = 0b11110111 ~pins_state & ... = 0b00000010 → OUTSET写入此值 → 第1位置1 pins_state & ... = 0b00000000 → OUTCLR写入此值 → 无引脚被清零 最终OUT寄存器值变为 0b00001010 这种实现方式的优势在于：
- 通过原子操作实现翻转，避免多线程 / 中断环境下的竞争条件
- 无需读取 – 修改 – 写入循环，执行效率高
- 仅用两条寄存器写入指令即可完成操作
寄存器组织概述
typedef struct { __IM uint32_t RESERVED[321]; // 地址偏移0x000-0x4FC：保留区域 __IOM uint32_t OUT; // 地址偏移0x504：端口输出值寄存器 __IOM uint32_t OUTSET; // 地址偏移0x508：端口置位寄存器 __IOM uint32_t OUTCLR; // 地址偏移0x50C：端口清零寄存器 __IM uint32_t IN; // 地址偏移0x510：端口输入值寄存器 __IOM uint32_t DIR; // 地址偏移0x514：端口方向控制寄存器 __IOM uint32_t DIRSET; // 地址偏移0x518：方向置位寄存器 __IOM uint32_t DIRCLR; // 地址偏移0x51C：方向清零寄存器 __IOM uint32_t LATCH; // 地址偏移0x520：输入状态锁存寄存器 __IOM uint32_t DETECTMODE; // 地址偏移0x524：检测模式寄存器 __IM uint32_t RESERVED1[118]; // 地址偏移0x528-0x6FC：保留区域 __IOM uint32_t PIN_CNF[32]; // 地址偏移0x700-0x77C：引脚配置数组 } NRF_GPIO_Type; 核心寄存器功能详解
- 输出控制寄存器组
OUT：直接控制所有引脚输出电平 (写 1 为高，写 0 为低)OUTSET：原子性置位引脚 (写 1 置高，写 0 无影响)OUTCLR：原子性清零引脚 (写 1 置低，写 0 无影响)
- 输入状态寄存器
IN：读取所有引脚当前的输入电平状态
- 方向控制寄存器组
DIR：直接控制所有引脚方向 (1 为输出，0 为输入)DIRSET：原子性设置引脚为输出模式DIRCLR：原子性设置引脚为输入模式
- 中断相关寄存器
LATCH：锁存满足 SENSE 配置的引脚状态DETECTMODE：配置中断触发模式 (电平 / 边沿)
- 引脚配置数组
PIN_CNF[32]：每个 GPIO 引脚对应一个 32 位配置字，可配置：- 输入缓冲器使能
- 上拉 / 下拉电阻
- 驱动能力
- 中断触发条件
设计亮点分析
- 原子操作设计
- OUTSET/OUTCLR 和 DIRSET/DIRCLR 寄存器允许无竞争的位操作
- 特别适合在多任务 / 中断环境中安全地操作单个引脚
- 内存映射优化
- 合理安排保留区域，确保寄存器地址与硬件实际地址匹配
- 32 个 PIN_CNF 寄存器连续排列，便于通过索引快速访问任意引脚配置
- 硬件特性映射
- LATCH 寄存器反映了硬件级的输入状态锁存功能
- DETECTMODE 支持灵活的中断触发配置
使用示例
以下是使用该结构体的典型代码片段：
// 设置P0.15为输出模式并置高 NRF_GPIO->DIRSET = (1UL << 15); NRF_GPIO->OUTSET = (1UL << 15); // 读取P0.23的输入状态 bool pin_state = (NRF_GPIO->IN & (1UL << 23)) != 0; // 配置P0.5为上拉输入并使能高电平检测 NRF_GPIO->PIN_CNF[5] = (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) | (GPIO_PIN_CNF_SENSE_High << GPIO_PIN_CNF_SENSE_Pos); 这种寄存器映射方式充分体现了嵌入式系统直接操作硬件的特点，为底层驱动开发提供了高效接口。
端口级操作函数
/** * @brief 设置端口引脚为输出模式 * @param p_reg 端口寄存器指针 * @param out_mask 输出掩码 */ __STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask) { p_reg->DIRSET = out_mask; } /** * @brief 读取端口输入值 * @param p_reg 端口寄存器指针 * @return 端口输入值 */ __STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg) { return p_reg->IN; } /** * @brief 设置端口引脚输出为高电平 * @param p_reg 端口寄存器指针 * @param set_mask 设置掩码 */ __STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask) { p_reg->OUTSET = set_mask; } 这些函数提供了端口级的批量操作能力，允许同时配置或读取多个引脚，提高了操作效率。
引脚存在性检查
/** * @brief 检查引脚是否存在 * @param[in] pin_number 引脚号 * @return true: 引脚存在, false: 引脚不存在 */ __STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number) { uint32_t port = pin_number >> 5; uint32_t mask = 0; switch (port) { #ifdef P0_FEATURE_PINS_PRESENT case 0: mask = P0_FEATURE_PINS_PRESENT; #if defined(NRF52820_XXAA) && defined(DEVELOP_IN_NRF52833) /* 允许使用额外的GPIOs */ mask |= 0x03003800; #endif break; #endif #ifdef P1_FEATURE_PINS_PRESENT case 1: mask = P1_FEATURE_PINS_PRESENT; break; #endif } pin_number &= 0x0F; return (mask & (1UL << pin_number)) ? true : false; } 这个函数用于检查指定的引脚是否在当前芯片上存在，通过查询芯片特定的 P0_FEATURE_PINS_PRESENT 和 P1_FEATURE_PINS_PRESENT 宏定义来实现。
代码设计特点与优势
- 分层设计：将硬件寄存器操作抽象为易于使用的函数接口
- 类型安全：使用枚举类型代替直接操作数值，提高代码可读性和健壮性
- 高效操作：通过内联函数实现，避免函数调用开销，提高执行效率
- 可配置性：通过条件编译支持不同型号的芯片和配置
- 错误检查：包含引脚存在性检查和断言，提高代码可靠性
使用示例
以下是使用该 GPIO 库的简单示例：
#include "nrf_gpio.h" int main(void) { // 配置P0.18为输出模式 nrf_gpio_cfg_output(18); // 配置P0.19为输入模式，带上拉电阻 nrf_gpio_cfg_input(19, NRF_GPIO_PIN_PULLUP); while (1) { // 读取P0.19的输入状态 if (nrf_gpio_pin_read(19)) { // 按钮按下，点亮LED nrf_gpio_pin_set(18); } else { // 按钮释放，熄灭LED nrf_gpio_pin_clear(18); } } } 总结
这段代码是 Nordic Semiconductor 为 nRF52 系列芯片设计的完整 GPIO 硬件抽象层，提供了从简单引脚操作到复杂端口配置的全面功能。通过内联函数实现和条件编译技术，代码在保证高效执行的同时，也具备了良好的可移植性和可配置性，是嵌入式系统中 GPIO 驱动设计的典范。
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