哈哈，一楼二楼说的很对，我直接给你写参考代码吧！reference_code.v

module reference_code (
    input clk;         //系统工作时钟
    input rst;         //系统复位信号，高电平有效
    input signal;      //外部设备输入信号
    output reg led;    //LED灯
);

// signal
reg  [2:0]  signal_reg;     //输入信号缓存
reg  [2:0]  negedge_cnt;    //下降沿计数

// 用FPGA内部时钟同步外部输入信号
always @ (posedge clk)
begin
    if (rst) begin
        signal_reg <= 3'd0;
    end
    else begin
        signal_reg[2:0] <= {signal_reg[1:0],signal};
    end
end

// 下降沿计数
always @ (posedge clk)
begin
    if (rst) begin
        negedge_cnt <= 3'd0;
    end
    else begin
        if (negedge_cnt == 3'd2) begin
            negedge_cnt <= 3'd0;
        end
        else if (signal_reg[2:1]==2'b10) begin
            negedge_cnt <= negedge_cnt + 1'b1;
        end
    end
end

// LED翻转
always @ (posedge clk)
begin
    if (rst) begin
        led <= 1'b0;
    end
    else begin
        if (negedge_cnt == 3'd2) begin
            led <= ~led;
        end
    end
end

endmodule