放置在硬IP引脚位置的PIPE x8 Gen1,Gen2和Gen3配置所需的Stratix V高级通道布局分配-Altera-Intel社区-FPGA CPLD-ChipDebug

放置在硬IP引脚位置的PIPE x8 Gen1,Gen2和Gen3配置所需的Stratix V高级通道布局分配

当放置在HardIP引脚位置时,PIPE PHY x8 Gen1,Gen2和Gen3配置需要提前通道布局分配。客户需要编辑.qsf文件。需要编辑两个参数才能解决滤波器错误。下面是参数。

I.主通道= 4

II。 reserve channel = true

解决/修复方法

set_parameter -name reserved_channel true -to“pipe_gen3_x8:pipe_gen3_x8_l | altera_xcvr_pipe:pipe_gen3_x8_inst | sv_xcvr_pipe_nr:pipe_nr_inst | sv_xcvr_pipe_native:transceiver_core”
set_parameter -name reserved_channel true -to“pipe_gen3_x8:pipe_gen3_x8_r | altera_xcvr_pipe:pipe_gen3_x8_inst | sv_xcvr_pipe_nr:pipe_nr_inst | sv_xcvr_pipe_native:transceiver_core”
set_parameter -name master_ch_number 4 -to“pipe_gen3_x8:pipe_gen3_x8_l | altera_xcvr_pipe:pipe_gen3_x8_inst | sv_xcvr_pipe_nr:pipe_nr_inst | sv_xcvr_pipe_native:transceiver_core”
set_parameter -name master_ch_number 4 -to“pipe_gen3_x8:pipe_gen3_x8_r | altera_xcvr_pipe:pipe_gen3_x8_inst | sv_xcvr_pipe_nr:pipe_nr_inst | sv_xcvr_pipe_native:transceiver_core”
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