mipi_d_phy_specification_v01-00-00.pdf
MIPI Alliance Specification for D-PHY
286 1 Overview
287 This specification provides a flexible, low-cost, High-Speed serial interface solution for communication
288 interconnection between components inside a mobile device. Traditionally, these interfaces are CMOS
289 parallel busses at low bit rates with slow edges for EMI reasons. The D-PHY solution enables significant
290 extension of the interface bandwidth for more advanced applications. The D-PHY solution can be realized
291 with very low power consumption.
292 1.1 Scope
293 The scope of this document is to specify the lowest layers of High-Speed source-synchronous interfaces to
294 be applied by MIPI Alliance application or protocol level specifications. This includes the physical
295 interface, electrical interface, low-level timing and the PHY-level protocol. These functional areas taken
296 together are known as D-PHY.
297 The D-PHY specification shall always be used in combination with a higher layer MIPI specification that
298 references this specification. Initially, this specification will be used for the connection of a host processor
299 to display and camera modules as used in mobile devices. However, this specification can also be
300 referenced by other upcoming MIPI Alliance specifications.
301 The following topics are outside the scope of this document:
302 • Explicit specification of signals of the clock generator unit. Of course, the D-PHY
303 specification does implicitly require some minimum performance from the clock signals.
304 Intentionally, only the behavior on the interface pins is constrained. Therefore, the clock
305 generation unit is excluded from this specification, and will be a separate functional unit that
306 provides the required clock signals to the D-PHY in order to meet the specification. This allows
307 all kinds of implementation trade-offs as long as these do not violate this specification. More
308 information can be found in section 4.
309 • Test modes, patterns, and configurations. Obviously testability is very important, but because
310 the items to test are mostly application specific or implementation related, the specification of
311 tests is deferred to either the higher layer specifications or the product specification. Furthermore
312 MIPI D-PHY compliance testing is not included in this specification.
313 • Procedure to resolve contention situations. The D-PHY contains several mechanisms to detect
314 Link contention. However, certain contention situations can only be detected at higher levels and
315 are therefore not included in this specification.
316 • Ensure proper operation of a connection between different Lane Module types. There are
317 several different Lane Module types to optimally support the different functional requirements of
318 several applications. This means that next to some base-functionality there are optional features
319 which can be included or excluded. This specification only ensures correct operation for a
320 connection between matched Lane Modules types, which means: Modules that support the same
321 features and have complementary functionality. In case the two sides of the Lane are not the same
322 type, and these are supposed to work correctly, it shall be ensured by the manufacturer(s) of the
323 Lane Module(s) that the provided additional functionality does not corrupt operation. This can be
324 easiest accomplished if the additional functionality can be disabled by other means independent of
325 the MIPI D-PHY interface, such that the Lane Modules behave as if they were the same type.
326 • ESD protection level of the IO. The required level will depend on a particular application
327 environment and product type.
没有回复内容