MIPI_DPHY2.0.pdf

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1 This specification provides a flexible, low-cost, High-Speed serial interface solution for communication 2 interconnection between components inside a mobile device. Traditionally, these interfaces are CMOS 3 parallel busses at low bit rates with slow edges for EMI reasons. The D-PHY solution enables significant 4 extension of the interface bandwidth for more advanced applications. The D-PHY solution can be realized 5 with very low power consumption.

MIPI_DPHY2.0.pdf

Contents
Contents……………………………………………………………………………………………………………. iii
Figures……………………………………………………………………………………………………………… vii
Tables…………………………………………………………………………………………………………………..x
Release History…………………………………………………………………………………………………. xii
1 Introduction …………………………………………………………………………………………………..1
1.1 Scope ……………………………………………………………………………………………………………….1
1.2 Purpose …………………………………………………………………………………………………………….2
2 Terminology …………………………………………………………………………………………………..3
2.1 Use of Special Terms………………………………………………………………………………………….3
2.2 Definitions………………………………………………………………………………………………………..3
2.3 Abbreviations…………………………………………………………………………………………………….4
2.4 Acronyms………………………………………………………………………………………………………….4
3 References……………………………………………………………………………………………………..6
4 D-PHY Overview……………………………………………………………………………………………7
4.1 Summary of PHY Functionality …………………………………………………………………………..7
4.2 Mandatory Functionality …………………………………………………………………………………….7
5 Architecture …………………………………………………………………………………………………..8
5.1 Lane Modules……………………………………………………………………………………………………8
5.2 Master and Slave………………………………………………………………………………………………..9
5.3 High Frequency Clock Generation ……………………………………………………………………….9
5.4 Clock Lane, Data Lanes and the PHY-Protocol Interface…………………………………………9
5.5 Selectable Lane Options……………………………………………………………………………………10
5.6 Lane Module Types ………………………………………………………………………………………….12
5.6.1 Unidirectional Data Lane ……………………………………………………………………………….13
5.6.2 Bi-directional Data Lanes……………………………………………………………………………….13
5.6.3 Clock Lane……………………………………………………………………………………………………14
5.7 Configurations…………………………………………………………………………………………………14
5.7.1 Unidirectional Configurations…………………………………………………………………………16
5.7.2 Bi-Directional Half-Duplex Configurations………………………………………………………17
5.7.3 Mixed Data Lane Configurations…………………………………………………………………….18
6 Global Operation………………………………………………………………………………………….19
6.1 Transmission Data Structure………………………………………………………………………………19
6.1.1 Data Units…………………………………………………………………………………………………….19
6.1.2 Bit order, Serialization, and De-Serialization…………………………………………………….19
6.1.3 Encoding and Decoding …………………………………………………………………………………19
6.1.4 Data Buffering………………………………………………………………………………………………19
6.2 Lane States and Line Levels………………………………………………………………………………19
6.3 Operating Modes: Control, High-Speed, and Escape …………………………………………….20
6.4 High-Speed Data Transmission ………………………………………………………………………….21
6.4.1 Burst Payload Data………………………………………………………………………………………..21
6.4.2 Start-of-Transmission …………………………………………………………………………………….21
6.4.3 End-of-Transmission ……………………………………………………………………………………..22
Specification for D-PHY Version 2.0
23-Nov-2015
iv Copyright © 2007-2016 MIPI Alliance, Inc.
All rights reserved.
Confidential
6.4.4 HS Data Transmission Burst……………………………………………………………………………22
6.5 Bi-directional Data Lane Turnaround………………………………………………………………….24
6.6 Escape Mode……………………………………………………………………………………………………27
6.6.1 Remote Triggers ……………………………………………………………………………………………28
6.6.2 Low-Power Data Transmission ……………………………………………………………………….28
6.6.3 Ultra-Low Power State …………………………………………………………………………………..29
6.6.4 Escape Mode State Machine …………………………………………………………………………..29
6.7 High-Speed Clock Transmission ………………………………………………………………………..31
6.8 Clock Lane Ultra-Low Power State…………………………………………………………………….36
6.9 Global Operation Timing Parameters………………………………………………………………….37
6.10 System Power States…………………………………………………………………………………………41
6.11 Initialization…………………………………………………………………………………………………….41
6.12 Calibration ………………………………………………………………………………………………………41
6.13 Global Operation Flow Diagram ………………………………………………………………………..45
6.14 Data Rate Dependent Parameters (informative)……………………………………………………47
6.14.1 Parameters Containing Only UI Values…………………………………………………………48
6.14.2 Parameters Containing Time and UI values…………………………………………………..48
6.14.3 Parameters Containing Only Time Values……………………………………………………..48
6.14.4 Parameters Containing Only Time Values That Are Not Data Rate Dependent…..49
6.15 Interoperability ………………………………………………………………………………………………..49
7 Fault Detection …………………………………………………………………………………………….50
7.1 Contention Detection………………………………………………………………………………………..50
7.2 Sequence Error Detection………………………………………………………………………………….50
7.2.1 SoT Error……………………………………………………………………………………………………..51
7.2.2 SoT Sync Error……………………………………………………………………………………………..51
7.2.3 EoT Sync Error……………………………………………………………………………………………..51
7.2.4 Escape Mode Entry Command Error………………………………………………………………..51
7.2.5 LP Transmission Sync Error……………………………………………………………………………51
7.2.6 False Control Error………………………………………………………………………………………..51
7.3 Protocol Watchdog Timers (informative) …………………………………………………………….51
7.3.1 HS RX Timeout…………………………………………………………………………………………….51
7.3.2 HS TX Timeout …………………………………………………………………………………………….51
7.3.3 Escape Mode Timeout ……………………………………………………………………………………51
7.3.4 Escape Mode Silence Timeout ………………………………………………………………………..51
7.3.5 Turnaround Errors …………………………………………………………………………………………52
8 Interconnect and Lane Configuration……………………………………………………………53
8.1 Lane Configuration…………………………………………………………………………………………..53
8.2 Boundary Conditions………………………………………………………………………………………..53
8.3 Definitions………………………………………………………………………………………………………53
8.4 S-parameter Specifications………………………………………………………………………………..54
8.5 Characterization Conditions ………………………………………………………………………………54
8.6 Interconnect Specifications………………………………………………………………………………..54
8.6.1 Differential Characteristics……………………………………………………………………………..55
8.6.2 Common-mode Characteristics……………………………………………………………………….57
8.6.3 Intra-Lane Cross-Coupling……………………………………………………………………………..57
8.6.4 Mode-Conversion Limits………………………………………………………………………………..57
8.6.5 Inter-Lane Cross-Coupling……………………………………………………………………………..57
Version 2.0 Specification for D-PHY
23-Nov-2015
Copyright © 2007-2016 MIPI Alliance, Inc. v
All rights reserved.
Confidential
8.6.6 Inter-Lane Static Skew …………………………………………………………………………………..58
8.7 Driver and Receiver Characteristics……………………………………………………………………59
8.7.1 Differential Characteristics……………………………………………………………………………..59
8.7.2 Common-Mode Characteristics……………………………………………………………………….60
8.7.3 Mode-Conversion Limits………………………………………………………………………………..61
9 Electrical Characteristics ……………………………………………………………………………..62
9.1 Driver Characteristics……………………………………………………………………………………….63
9.1.1 High-Speed Transmitter………………………………………………………………………………….63
9.1.2 Low-Power Transmitter………………………………………………………………………………….69
9.2 Receiver Characteristics ……………………………………………………………………………………72
9.2.1 High-Speed Receiver……………………………………………………………………………………..72
9.2.2 Low-Power Receiver……………………………………………………………………………………..74
9.3 Line Contention Detection…………………………………………………………………………………75
9.4 Input Characteristics…………………………………………………………………………………………76
10 High-Speed Data-Clock Timing………………………………………………………………….78
10.1 High-Speed Clock Timing …………………………………………………………………………………78
10.2 Forward High-Speed Data Transmission Timing ………………………………………………….79
10.2.1 Data-Clock Timing Specifications………………………………………………………………..80
10.2.2 Normative Spread Spectrum Clocking (SSC) ………………………………………………..81
10.2.3 Transmitter Eye Diagram Specification ………………………………………………………..82
10.2.4 Receiver Eye Diagram Specification…………………………………………………………….84
10.3 Reverse High-Speed Data Transmission Timing …………………………………………………..85
10.4 Operating Modes: Data rate and Channel Support Guidance………………………………….86
11 Regulatory Requirements…………………………………………………………………………..88
12 Built-In HS Test Mode (Informative)………………………………………………………….89
12.1 Introduction……………………………………………………………………………………………………..89
12.2 Entering the HS Test Mode………………………………………………………………………………..90
12.3 HS Test Mode ………………………………………………………………………………………………….90
12.4 Special Case: Multi-Lane Testing……………………………………………………………………….92
12.5 Exiting from HS Test Mode……………………………………………………………………………….92
Annex A Logical PHY-Protocol Interface Description (informative)……………….93
A.1 Signal Description ……………………………………………………………………………………………93
A.2 High-Speed Transmit from the Master Side ……………………………………………………….103
A.3 High-Speed Receive at the Slave Side……………………………………………………………….104
A.4 High-Speed Transmit from the Slave Side …………………………………………………………104
A.5 High-Speed Receive at the Master Side …………………………………………………………….105
A.6 Low-Power Data Transmission…………………………………………………………………………105
A.7 Low-Power Data Reception……………………………………………………………………………..106
A.8 Turn-around …………………………………………………………………………………………………..106
A.9 Calibration …………………………………………………………………………………………………….107
A.10 Optical Link Support ………………………………………………………………………………………109
A.10.1 System Setup …………………………………………………………………………………………..109
A.10.2 Serializer and De-Serializer Block Diagrams……………………………………………….110
A.10.3 Timing Constraints…………………………………………………………………………………..111
A.10.4 System Constraints…………………………………………………………………………………..112
Specification for D-PHY Version 2.0
23-Nov-2015
vi Copyright © 2007-2016 MIPI Alliance, Inc.
All rights reserved.
Confidential
Annex B Interconnect Design Guidelines (informative) ………………………………..113
B.1 Practical Distances………………………………………………………………………………………….113
B.2 RF Frequency Bands: Interference ……………………………………………………………………113
B.3 Transmission Line Design ……………………………………………………………………………….113
B.4 Reference Layer……………………………………………………………………………………………..113
B.5 Printed-Circuit Board………………………………………………………………………………………114
B.6 Flex-foils……………………………………………………………………………………………………….114
B.7 Series Resistance ……………………………………………………………………………………………114
B.8 Connectors…………………………………………………………………………………………………….114
Annex C 8b9b Line Coding for D-PHY (normative)……………………………………..115
C.1 Line Coding Features………………………………………………………………………………………116
C.1.1 Enabled Features for the Protocol ………………………………………………………………116
C.1.2 Enabled Features for the PHY……………………………………………………………………116
C.2 Coding Scheme………………………………………………………………………………………………116
C.2.1 8b9b Coding Properties…………………………………………………………………………….116
C.2.2 Data Codes: Basic Code Set………………………………………………………………………116
C.2.3 Comma Codes: Unique Exception Codes ……………………………………………………117
C.2.4 Control Codes: Regular Exception Codes……………………………………………………118
C.2.5 Complete Coding Scheme …………………………………………………………………………118
C.3 Operation with the D-PHY ………………………………………………………………………………118
C.3.1 Payload: Data and Control…………………………………………………………………………118
C.3.2 Details for HS Transmission………………………………………………………………………119
C.3.3 Details for LP Transmission ………………………………………………………………………119
C.4 Error Signaling……………………………………………………………………………………………….120
C.5 Extended PPI …………………………………………………………………………………………………120
C.6 Complete Code Set …………………………………………………………………………………………121

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