mipi_DSI-2_specification_v1-0.pdf
4 DSI-2 Introduction
234 DSI-2 specifies the interface between a Host Processor and a peripheral, such as a display module. It builds
235 on existing MIPI Alliance Specifications by adopting pixel formats and the command set specified in the
236 DPI-2, DBI-2 and DCS standards. From a conceptual viewpoint, a DSI-2-compliant interface performs the
237 same functions as interfaces based on the DBI-2 and DPI-2 standards or similar parallel display interfaces. It
238 sends pixels or commands to the peripheral, and can read back status or pixel information from the peripheral.
239 The main difference is that DSI serializes all pixel data, commands, and events that, in traditional or legacy
240 interfaces, are normally conveyed to and from the peripheral on a parallel data bus with additional control
241 signals.
242 From a system or software point of view, the serialization and deserialization operations should be
243 transparent. The most visible, and unavoidable, consequence of transformation to serial data and back to
244 parallel is increased latency for transactions that require a response from the peripheral. For example, reading
245 a pixel from the frame buffer on a display module has a higher latency using DSI-2 than DBI. Another
246 fundamental difference is the Host Processor’s inability during a read transaction to throttle the rate, or size,
247 of returned data.
248 Two high-speed serial data Transmission interface options are defined.
249 The first high-speed data Transmission interface option, referred to in this Specification as the D Option, is
250 a high-speed differential interface with one 2-wire clock Lane and one or more 2-wire data Lanes. The
251 physical layer of this interface is defined by the MIPI Alliance Specification for D-PHY [MIPI04] or
252 [MIPI08]. Figure 1 illustrates the connections for the D Option between a Host device and peripheral.
Host Device, e.g. an Application
Processor or Baseband Processor
containing HS Transmitter, LP
Transmitter, LP Receiver
Peripheral, e.g. a Display containing HS
Receiver, LP Receiver, optional LP
Transmitter (for bidirectional only)
DataN+
DataNClock+
ClockData0+
Data0- Number of Data
Lanes may be
1, 2, 3, or 4
DataN+
DataNClock+
ClockData0+
Data0-
High Speed
Data Links
(Lane 0 may be
bidirectional in
LP Mode)
253
254 Figure 1 DSI Transmitter and Receiver Interface (D Option)
Version 1.0 Specification for DSI-2
17-Nov-2015
Copyright © 2005-2016 MIPI Alliance, Inc. 11
All rights reserved.
Confidential
255 The second option, referred to in this Specification as the C Option, consists of one or more 3-wire serial data
256 Lanes, each of which has its own embedded clock. The physical layer of this interface is defined by [MIPI07].
257 Figure 2 illustrates the connections for the C Option between a Host device and peripheral, which typically
258 are an application processor and a display module, part of the mobile phone engine. When Lane 0 is in LP
259 mode, Data0_B shall be driven to the LP low state by the same end of the Link that is driving the Data0_A
260 and Data0_C lines.
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