verilog VHDL中的状态机设计技巧

Abstract†
: Designing a synchronous finite state
machine (FSM) is a common task for a digital logic
engineer. This paper will discuss a variety of issues
regarding FSM design using Synopsys Design
Compiler1. Verilog and VHDL coding styles will be
presented. Different methodologies will be compared
using real-world examples.
1.0 Introduction
A finite state machine2 has the general structure
shown in Figure 1.
The current state of the machine is stored in the
state memory, a set of n flip-flops clocked by a
single clock signal (hence “synchronous” state
machine). The state vector (also current state, or
just state) is the value currently stored by the state
memory. The next state of the machine is a function
of the state vector and the inputs. Mealy outputs [7]
are a function of the state vector and the inputs
while Moore outputs [8] are a function of the state
vector only.
Another way of organizing a state machine uses
only one logic block as shown in Figure 2.
2.0 Basic HDL coding
The logic in a state machine is described using a
case statement or the equivalent (e.g. if-else).
All possible combinations of current state and
inputs are enumerated and the appropriate values
are specified for next state and the outputs.
A state machine may be coded as per Figure 1 using
two separate case statements, or following Figure
2 using only one. A single case statement may be
preferred for Mealy machines where the outputs
depend on the state transition rather than just the
current state.
The listings in the Appendix show examples of both
techniques. prep3 uses a single case whereas prep4
is coded with a separate logic block that generates
the outputs.
Here are a few general rules to follow:
• Only one state machine per module
• Keep extraneous logic at a minimum (i.e. try not
to put other code in the same module as the FSM —
this is especially important if you use extract)
• Instantiate state flops separately from logic
3.0 State assignment
Usually the most important decision to make when
designing a state machine is what state encoding to
use. A poor choice of codes will result in a state
machine that uses too much logic, or is too slow, or
both.
Many tools and techniques have been developed for
choosing an “optimal” state assignment. Typically
such approaches use the minimum number of state
bits [10] or assume a two-level logic
implementation such as a PLA [3]. Only recently
has work been done on the multi-level logic
synthesis typical of gate array design [1].
3.1 Highly-encoded state assignment
A highly-encoded state assignment will use fewer
flops for the state vector, however additional logic