FPGA SATA开发资料 SATA Storage Technology.pdf 分享

ContentsixAbout This BookScope……………………………………………………………………………………………………………………………1The MindShare Architecture Series ……………………………………………………………………………1Cautionary Note ………………………………………………………………………………………………………….3The Standard Is the Final Word ………………………………………………………………………………….3Documentation Conventions………………………………………………………………………………………3Hexadecimal Notation …………………………………………………………………………………………..3Binary Notation……………………………………………………………………………………………………..4Decimal Notation …………………………………………………………………………………………………..4Bits Versus Bytes Notation …………………………………………………………………………………….4Bit Fields ………………………………………………………………………………………………………………..4Other Terminology and Abbreviations ………………………………………………………………………5Visit Our Web Site (www.mindshare.com) ……………………………………………………………….. 5We Want Your Feedback……………………………………………………………………………………………..6Part OneSATA OverviewChapter 1: The Evolution of Parallel ATAATA transitions to Serial Interface……………………………………………………………………………..9Origins of ATA ………………………………………………………………………………………………………….10Emergence of IDE (Integrated Disc Electronics) Drives…………………………………………… 11Support for Two Drives ……………………………………………………………………………………….11Compatibility Problems ……………………………………………………………………………………….12The ATA Standard …………………………………………………………………………………………………….12The ATA Signalling Interface……………………………………………………………………………….13ATA Protocol/Performance Review…………………………………………………………………….17ATA……………………………………………………………………………………………………………….17ATA-2/3………………………………………………………………………………………………………..17ATA-4 ……………………………………………………………………………………………………………18ATA-5 ……………………………………………………………………………………………………………18ATA-6 ……………………………………………………………………………………………………………18ATA-7 ……………………………………………………………………………………………………………18The Legacy Programming Interface…………………………………………………………………………..19HBA Register Descriptions…………………………………………………………………………………..20Device Register – Selecting the Target ATA Device………………………………………..21Start Sector Address ………………………………………………………………………………………21Physical Disc Address Registers………………………………………………………………22Logical Block Addressing………………………………………………………………………..24Logical Block Address Registers (28 bits) ………………………………………………..24

ContentsxLogical Block Address Registers (48 bits) ………………………………………………..24Transfer Size Register…………………………………………………………………………………….25Feature Register …………………………………………………………………………………………….25Command Register………………………………………………………………………………………..26Data Register …………………………………………………………………………………………………26Status Register ……………………………………………………………………………………………….26Error Register ………………………………………………………………………………………………..28Device Control Register …………………………………………………………………………………28Alternate Status Register ……………………………………………………………………………….29Support for Multiple ATA Interfaces……………………………………………………………………29The ATA Packet Interface (ATAPI)…………………………………………………………………………..30Device Signature ……………………………………………………………………………………………………….31Performing Commands……………………………………………………………………………………………..31Setting Up Data Transfers ……………………………………………………………………………..32Commands without Data Transfer ………………………………………………………….32Data Transfer Commands. ………………………………………………………………………32Command Execution……………………………………………………………………………………..32Overlap and Command Queuing…………………………………………………………………………34Overlap………………………………………………………………………………………………………….34Queuing…………………………………………………………………………………………………………35Drives Capabilities – The Device Identify Command…………………………………………… 35Summary of ATA Standards……………………………………………………………………………………..36Chapter 2: The Motivation for SATAMotivation and Design Goals for SATA…………………………………………………………………..37Lower Pin Count………………………………………………………………………………………………………..38Performance……………………………………………………………………………………………………………….38No Drive Configuration Required…………………………………………………………………………….39Cables and Connectors………………………………………………………………………………………………39Reliability ………………………………………………………………………………………………………………….41Lower Voltages ………………………………………………………………………………………………………….41Migration to Servers ………………………………………………………………………………………………….41Software Compatibility with Parallel ATA ………………………………………………………………42Chapter 3: SATA OverviewThe SATA Specification ……………………………………………………………………………………………43Summary of SATA Features ……………………………………………………………………………………..44The Serial Interconnect ……………………………………………………………………………………………..45SATA Compatibility with Parallel ATA …………………………………………………………………..46The Legacy Programming Interface……………………………………………………………………..46Legacy Drive Addressing with SATA …………………………………………………………………. 48

ContentsxiDrive Addressing Based on Single Drive Interfaces……………………………………….49Port Selection Based on Master/Slave Emulation ………………………………………….49SATA-Specific Registers …………………………………………………………………………………………..51SATA Protocol Layer Overview ………………………………………………………………………………..52Application Layer ………………………………………………………………………………………………..53Host Software Issues each Command ……………………………………………………………54The SATA Drive Receives and Processes the Command ………………………………. 55Command Layer ………………………………………………………………………………………………….55Transport Layer……………………………………………………………………………………………………55Link Layer………………………………………………………………………………………………………………….57Physical Layer ……………………………………………………………………………………………………………58Establishing Link Communications ……………………………………………………………………..59OOB Signaling……………………………………………………………………………………………….59Link initialization…………………………………………………………………………………………..61Normal FIS Communications……………………………………………………………………………….61SATA Command Protocol …………………………………………………………………………………………61Example Non-Data Command……………………………………………………………………………..62Example DMA Read Command …………………………………………………………………………..63Example DMA Write Command ………………………………………………………………………….64Major Features of SATA II ………………………………………………………………………………………..65Native Command Queuing ………………………………………………………………………………….65Port Multipliers ……………………………………………………………………………………………………66Port Selectors ……………………………………………………………………………………………………….67Enclosure Services………………………………………………………………………………………………..68Hot Plug Support …………………………………………………………………………………………………69Higher Transmission Rate ……………………………………………………………………………………69The AHCI Programming Interface ……………………………………………………………………………69Chapter 4: Introduction to FIS TransfersGeneral ………………………………………………………………………………………………………………………71FIS Transfers ……………………………………………………………………………………………………………..72Application Layer (HBA)……………………………………………………………………………………..73Transport Layer (HBA) ………………………………………………………………………………………..73Frame Information Structures………………………………………………………………………..75FIS Ready for Transfer …………………………………………………………………………………..75Flow Control During FIS Transmission …………………………………………………………76Link Layer (Transmit) ………………………………………………………………………………………….76CRC Generation …………………………………………………………………………………………….77Framing the FIS ……………………………………………………………………………………………..78Scrambler ………………………………………………………………………………………………………78Perform 8b-to-10b encoding…………………………………………………………………………..79Physical Layer (Transmit)…………………………………………………………………………………….79

ContentsxiiFIS Transmission……………………………………………………………………………………………79Physical Layer (Receive) ………………………………………………………………………………………80Link Layer (Receive)…………………………………………………………………………………………….80Arbitration …………………………………………………………………………………………………….818b-to-10b Decoding………………………………………………………………………………………..82Un-Scrambling ………………………………………………………………………………………………82Detecting the FIS ……………………………………………………………………………………………82CRC Check…………………………………………………………………………………………………….82Transport Layer (Receive)…………………………………………………………………………………….82Command and Application Layers (Receive)……………………………………………………….82Part TwoFIS Transmission ProtocolsChapter 5: FIS Types and FormatsGeneral ………………………………………………………………………………………………………………………85Register FIS – Host to Device …………………………………………………………………………………….86Register FIS – Device to Host …………………………………………………………………………………….89Set Device Bits FIS…………………………………………………………………………………………………….92Set Device Bits with Active Field………………………………………………………………………….94Set Device Bits with Event Notification………………………………………………………………..94PIO Setup FIS ……………………………………………………………………………………………………………95DMA Setup FIS …………………………………………………………………………………………………………96First Party DMA Setup…………………………………………………………………………………………97DMA Setup with Auto Activate …………………………………………………………………………..98DMA Activate FIS……………………………………………………………………………………………………..99DATA FIS ………………………………………………………………………………………………………………..100BIST Activate FIS …………………………………………………………………………………………………….100Chapter 6: Transport and Link ProtocolsOverview………………………………………………………………………………………………………………….103FIS Transmission……………………………………………………………………………………………………..105Primitive Generation – FIS Transmitter ………………………………………………………………106FIS Transmission Buffer……………………………………………………………………………………..108FIS Arbitration……………………………………………………………………………………………………108CRC Generation …………………………………………………………………………………………………110Framing Each FIS (SOF and EOF) ………………………………………………………………………110FIS Scrambling……………………………………………………………………………………………………111Repeated Primitive Suppression…………………………………………………………………………113CONT Primitive …………………………………………………………………………………………..114Repeated Primitive Scrambler ……………………………………………………………………..115

Contentsxiii8b/10b Encoding………………………………………………………………………………………………..116General ………………………………………………………………………………………………………..116Purpose of Encoding a value Stream ……………………………………………………………116The 8b to 10b Conversion …………………………………………………………………………….116Current Running Disparity ………………………………………………………………………….116FIS Reception …………………………………………………………………………………………………………..117Primitive Generation – FIS Receiver……………………………………………………………………1188b/10b Decode …………………………………………………………………………………………………..119Error Detection…………………………………………………………………………………………….120Primitive Suppression Detection ………………………………………………………………………..121FIS Unscrambling……………………………………………………………………………………………….121Detecting FIS………………………………………………………………………………………………………121CRC Check …………………………………………………………………………………………………………121FIS Decode …………………………………………………………………………………………………………121Summary of FIS Transfer Protocol …………………………………………………………………………122Chapter 7: FIS RetryGeneral …………………………………………………………………………………………………………………….125Which FISes Can be Retried?…………………………………………………………………………………..126Retry Protocol Overview………………………………………………………………………………………….127What Errors Result in Retry Attempts?…………………………………………………………………… 128Transmission Errors — Detected by Link Layer ………………………………………………… 129Other FIS errors — Detected by Transport Layer ………………………………………………130Internal Transport Layer Errors……………………………………………………………………131FIS Errors……………………………………………………………………………………………………..131The Retry State Machine …………………………………………………………………………………………131Chapter 8: Data Flow ControlOverview………………………………………………………………………………………………………………….134Flow Control by Transmitter …………………………………………………………………………………..134Flow Control Protocol (Transmitter Initiated)…………………………………………………….136Dry Condition Results in HOLD ………………………………………………………………….136Receiver Acknowledges HOLD……………………………………………………………………136Buffer Nearly Full and Hold Released …………………………………………………………138Receiver Detects Data and Releases HOLDA……………………………………………….138Protocol Example…………………………………………………………………………………………138Flow Control by Receiver ………………………………………………………………………………………..140Flow Control Protocol (Receiver Initiated) …………………………………………………………140Buffer Nearly Full Results in HOLD…………………………………………………………….140Transmitter Recognizes HOLD request and Returns HOLDA…………………….. 140Receive Buffer Nears Empty and HOLD Released………………………………………. 142

ContentsxivTransmitting Node Resumes Data Transfer …………………………………………………142HOLD/HOLDA Propagation Delay…………………………………………………………………..142Receiving Node HOLD Transmission Delay……………………………………………….. 144HOLD to HOLDA Round Trip Delay…………………………………………………………..146Receiver Initiated Hold Example …………………………………………………………………149Chapter 9: Physical Layer FunctionsIntroduction……………………………………………………………………………………………………………..151Differential Transmitter/Receiver …………………………………………………………………………..153Transmitter Characteristics…………………………………………………………………………………153Receiver Characteristics ……………………………………………………………………………………..154Clock Management………………………………………………………………………………………………….155Local Clock Frequency ……………………………………………………………………………………….155Clock Accuracy ……………………………………………………………………………………………156Spread-Spectrum Clocking…………………………………………………………………………..156Data Extraction…………………………………………………………………………………………….156Double Word (DWord) Detection ………………………………………………………………..157Clock Compensation ……………………………………………………………………………………157Chapter 10: Error Detection and HandlingScope of SATA Error Checking……………………………………………………………………………….159Error Reporting — HBA Versus SATA Drives………………………………………………………..161Error Reporting and Handling Mechanisms ………………………………………………………….. 161ATA Compatible Registers…………………………………………………………………………………163ATA Status Register …………………………………………………………………………………….163ATA Error Register………………………………………………………………………………………164SATA-Specific Error Related Registers……………………………………………………………….164SATA Status (SStatus) Register…………………………………………………………………….164SATA Error (SError) Register……………………………………………………………………….165The Error Field ………………………………………………………………………………………165The Diagnostic Field………………………………………………………………………………166Error Detection and Recovery Mechanisms……………………………………………………………. 167CRC Checks ……………………………………………………………………………………………………….167Disparity Error Checks……………………………………………………………………………………….167Time-outs …………………………………………………………………………………………………………..168Layer-Specific Errors and Actions …………………………………………………………………………..168Physical Layer Errors …………………………………………………………………………………………168No Device Present Error ………………………………………………………………………………168OOB Signaling Errors…………………………………………………………………………………..169PHY Internal Errors……………………………………………………………………………………..170Link Layer Errors ……………………………………………………………………………………………….171

Contentsxv8b/10b Encoding and Decoding Errors………………………………………………………..171Disparity Errors within FISes ………………………………………………………………..172Disparity Errors within Primitives…………………………………………………………172CRC Errors…………………………………………………………………………………………………..172ATA Error Status …………………………………………………………………………………..173Link Sequence Errors …………………………………………………………………………………..173Transport Layer Errors……………………………………………………………………………………….174Frame Errors………………………………………………………………………………………………..174Transport State Transition/Protocol Errors………………………………………………….174Internal Transport Layer Errors……………………………………………………………………174Part ThreeCommand and Control ProtocolsChapter 11: The Command ProtocolOverview………………………………………………………………………………………………………………….177Command Types ……………………………………………………………………………………………………..178Command Delivery………………………………………………………………………………………………….179Command Transport to Disc Drive…………………………………………………………………….179Command Reception………………………………………………………………………………………….180Recognizing and Decoding the Command …………………………………………………………182Command Not Implemented …………………………………………………………………………………..183Non-Data Commands………………………………………………………………………………………………184PIO Commands ……………………………………………………………………………………………………….187PIO Data-In Commands……………………………………………………………………………………..188Parallel ATA PIO Data-In Review………………………………………………………………..189SATA PIO Data-In Command Protocol Overview ………………………………………. 189SATA Device PIO Data-In Command Protocol …………………………………………… 191PIO_IN State………………………………………………………………………………………….191Send PIO Setup State……………………………………………………………………………..191Transmit Data State ……………………………………………………………………………….192Error State ……………………………………………………………………………………………..192PIO Setup FIS Received …………………………………………………………………………193Data FIS Received………………………………………………………………………………….193PIO Data Out Commands…………………………………………………………………………………..194Parallel ATA PIO Data-Out Review …………………………………………………………….196SATA PIO Data-Out Command Protocol Overview……………………………………. 197SATA Device PIO Data-Out Command Protocol ………………………………………… 198PIO_Out State………………………………………………………………………………………..199Send PIO Setup State……………………………………………………………………………..199Receive Data State …………………………………………………………………………………199

ContentsxviPIO Out State…………………………………………………………………………………………200HBA PIO Data-Out Command Protocol ………………………………………………………200PIO Setup FIS Received …………………………………………………………………………200Data Received from Host ………………………………………………………………………200Register FIS Received…………………………………………………………………………….200DMA Commands …………………………………………………………………………………………………….201DMA-In Protocol………………………………………………………………………………………………..202Device DMA-In Command Protocol…………………………………………………………….203Host DMA-In Command Protocol ……………………………………………………………….204Data FIS Detected ………………………………………………………………………………….204Register FIS Detected …………………………………………………………………………….205Write DMA…………………………………………………………………………………………………………206Device’s Write DMA Protocol………………………………………………………………………208Host’s Write DMA Command Protocol ……………………………………………………….209DMA Queued Commands………………………………………………………………………………….210DMA Queued Command Concepts……………………………………………………………..210Register Definition for Queued Commands………………………………………………… 210Queued Command Initialization …………………………………………………………..210Service Request ……………………………………………………………………………………..211DMA-In Queued Command Protocol Overview ……………………………………………….. 212DMA-Out Queued Command Protocol Overview…………………………………………….. 214First Party DMA Commands……………………………………………………………………………………216Packet Command Protocol ………………………………………………………………………………………216Device Reset Command Protocol…………………………………………………………………………….218Execute Device Diagnostic ………………………………………………………………………………………219Chapter 12: Control ProtocolWrite Control Protocol …………………………………………………………………………………………….221Device Control Register Functions………………………………………………………………………….223Interrupt Enable (nIEN) Control Protocol………………………………………………………………. 223Software Reset (SRST) …………………………………………………………………………………………….224Part FourSATA IIChapter 13: SATA II FeaturesOverview………………………………………………………………………………………………………………….229Performance and Reliability ……………………………………………………………………………………230Generation 2 Transmission Rates ……………………………………………………………………….230Native Command Queuing ………………………………………………………………………………..230Asynchronous Signal Recovery ………………………………………………………………………….231

ContentsxviiEnhanced Support for Server Applications ……………………………………………………………. 231Port Multipliers ………………………………………………………………………………………………….231Port Selectors ……………………………………………………………………………………………………..232Multilane Cables ………………………………………………………………………………………………..233Hot Plug …………………………………………………………………………………………………………….234Enclosure Services………………………………………………………………………………………………234Reporting/Detecting Feature Support…………………………………………………………………….. 234Chapter 14: Native Command QueuingOverview………………………………………………………………………………………………………………….235The Problem – Limited Performance…………………………………………………………………..236Queuing Helps …………………………………………………………………………………………………..236Native Command Queuing is Better…………………………………………………………………..236System Support Requirements………………………………………………………………………………..238NCQ Drive Support……………………………………………………………………………………………239New Commands ………………………………………………………………………………………………..241First Party DMA Read Command……………………………………………………………….. 241First Party DMA Write Command……………………………………………………………….242Queue Management …………………………………………………………………………………………..242The Software Command Queue …………………………………………………………………..242Programming the DMA Transfer …………………………………………………………………244Tracking Pending Commands ……………………………………………………………………………245SATA Active Register ………………………………………………………………………………….246Set Device Bits FIS………………………………………………………………………………………..246First Party DMA Command Protocol ……………………………………………………………………… 247FPDMA Read Protocol Overview ………………………………………………………………………247FPDMA Write Protocol Overview………………………………………………………………………249Auto-Activate Feature………………………………………………………………………………………..251Auto-Activate with Single Data FIS ……………………………………………………………..251Auto-Activate with Multiple Data FISs………………………………………………………..252Detecting and Enabling Auto-Activation Support ………………………………………. 253Supporting Non-Zero Offsets………………………………………………………………………………….254Chapter 15: Port MultipliersOverview………………………………………………………………………………………………………………….257Port Multiplier Port Addresses………………………………………………………………………………..259Frame Routing …………………………………………………………………………………………………………260Device Port Numbers …………………………………………………………………………………………261FIS Transmission……………………………………………………………………………………………………..262FIS Transmission HBA to Drive………………………………………………………………………….262Error Free FIS Transfer…………………………………………………………………………………262

ContentsxviiiPM Error Detection and Handling – HBA FIS Delivery……………………………….. 263FIS Transmission Drive to HBA………………………………………………………………………….263Error Free FIS Transmission…………………………………………………………………………264PM Error Detection and Handling – Device FIS Delivery…………………………….. 264Collisions……………………………………………………………………………………………………………265Background Information ……………………………………………………………………………..265Handling Collisions……………………………………………………………………………………..265Device Port Registers……………………………………………………………………………………………….266Port Status and Control Registers……………………………………………………………………….267SStatus Register – PSCR [0]…………………………………………………………………………..267SError Register – PSCR [1] ……………………………………………………………………………268SControl Register – PSCR [2] ………………………………………………………………………..269Port Event Counters – Port SCR [257-2303]…………………………………………………..269PHY Event Counter Identifiers………………………………………………………………270PHY Event Counter Size………………………………………………………………………..271Vendor-Specific PHY Event Counters Identifiers………………………………….. 271Local PM Port …………………………………………………………………………………………………….271Local Port Registers ……………………………………………………………………………………………272PM Initialization ……………………………………………………………………………………………………..274PM Power-up State …………………………………………………………………………………………….274Detecting PM Presence……………………………………………………………………………………….274Configuring Device Ports …………………………………………………………………………………..275PM Read and Write Commands………………………………………………………………………………276PM Read Command …………………………………………………………………………………………..276Command Setup ………………………………………………………………………………………….276PM Register Read Command with Good Status………………………………………….. 278PM Register Read Command with Error Status ………………………………………….. 279PM Write Command ………………………………………………………………………………………….280Command Setup ………………………………………………………………………………………….280PM Register Write Command with Good Status…………………………………………. 282Hot Plug Support …………………………………………………………………………………………………….284Staggered Spinup/Drive Activity Indicator……………………………………………………………. 284Staggered Spinup……………………………………………………………………………………………….284Drive Activity …………………………………………………………………………………………………….285Chapter 16: Port SelectorsOverview………………………………………………………………………………………………………………….287Port Selector Functions ……………………………………………………………………………………………289Detecting Port Selector Presence……………………………………………………………………………..290Port Selection …………………………………………………………………………………………………………..291The Active Port at Startup ………………………………………………………………………………….292The Pre-Selected Active Port………………………………………………………………………..292

ContentsxixDynamic Active Port Selection …………………………………………………………………….292OOB Protocol Switching …………………………………………………………………………………….292Side-Band Signal Switching………………………………………………………………………………..294Chapter 17: Enclosure ServicesOverview………………………………………………………………………………………………………………….295Enclosure Services……………………………………………………………………………………………………297SAF-TE (SCSI Attached Fault-Tolerant Enclosure)……………………………………………..297SES (SCSI Enclosure Services)…………………………………………………………………………….297SATA Storage Enclosure Services Commands……………………………………………………….. 297Topologies ……………………………………………………………………………………………………………….299Part FivePhysical Layer DetailsChapter 18: SATA InitializationIntroduction……………………………………………………………………………………………………………..303Hardware Initialization …………………………………………………………………………………………..305General……………………………………………………………………………………………………………….305The Physical Plant………………………………………………………………………………………………306Physical Plant Signal Definitions………………………………………………………………….306OOB (Out of Band) Signaling …………………………………………………………………………………307Special Note Regarding OOB Timing and Terms ………………………………………………. 308OOB — Transmission…………………………………………………………………………………………308OOB — Reception ………………………………………………………………………………………………310OOB Protocol Sequence ……………………………………………………………………………………..311Avoiding Confusion…………………………………………………………………………………….311Device Detection ………………………………………………………………………………………….312Optional Calibration…………………………………………………………………………………….312OOB Problems……………………………………………………………………………………………..313Speed Negotiation………………………………………………………………………………………………313Roles During Speed Negotiation………………………………………………………………….313D10.2 Used as a “Dial Tone” ………………………………………………………………………..314Speed Negotiation Example ……………………………………………………………………………….314Asynchronous Signal Recovery ………………………………………………………………………….316Host Phy Asynchronous Signal Recovery ……………………………………………………316Host Phy Sends COMRESET …………………………………………………………………316Unsolicited COMINIT……………………………………………………………………………316Software Initialization …………………………………………………………………………………………….317

ContentsxxChanges for SATA II ……………………………………………………………………………………………….318Port Multiplier……………………………………………………………………………………………………318PM Default Active Port………………………………………………………………………………..319PM Discovery ………………………………………………………………………………………………319Enabling PM Ports ……………………………………………………………………………………….319Port Selector ……………………………………………………………………………………………………….321Chapter 19: Physical LayerIntroduction……………………………………………………………………………………………………………..325Logical Interface ………………………………………………………………………………………………………326Transmit Side……………………………………………………………………………………………………..327Selecting Frames or OOB Primitives…………………………………………………………….328Reducing EMI by Using SSC………………………………………………………………………..328Bit Frequency……………………………………………………………………………………………….330Receive Block ……………………………………………………………………………………………………..330Recovering the Clock………………………………………………………………………………………….331Tracking Architecture ………………………………………………………………………………….332Non-Tracking (Oversampling) Architecture ………………………………………………..334Clock Compensation ………………………………………………………………………………………….335Achieving Dword Synchronization ……………………………………………………………..337Implementation Example ………………………………………………………………………………………..338Power Management …………………………………………………………………………………………………339Electrical Interface……………………………………………………………………………………………………340Differential Signaling …………………………………………………………………………………………340Common-Mode Noise Rejection…………………………………………………………………..340Other Advantages of Differential signaling………………………………………………….343Transmission Characteristics………………………………………………………………………………343Eye Diagram ………………………………………………………………………………………………………347Signal Compensation………………………………………………………………………………………….350De-emphasis ………………………………………………………………………………………………..350Overcoming ISI ……………………………………………………………………………………………350Equalization…………………………………………………………………………………………………353Comparing the Methods………………………………………………………………………………354Extreme Signalling Environments…………………………………………………………………………..354Direct Versus AC Coupling………………………………………………………………………………..354Drive Electrical Interface…………………………………………………………………………………….355HBAs Manage Extreme Environments……………………………………………………………….355Electrical Parameters ………………………………………………………………………………………….355SAPIS …………………………………………………………………………………………………………………356

ContentsxxiChapter 20: Cables & ConnectorsIntroduction……………………………………………………………………………………………………………..361Usage Models and Form Factors ……………………………………………………………………………..362Cables and Connectors — A Review………………………………………………………………………. 363The SATA Device Connector ……………………………………………………………………………..363Internal cables and connectors……………………………………………………………………………365Single Lane Cables……………………………………………………………………………………….366Multiple-lane Cables ……………………………………………………………………………………368Backplane connectors…………………………………………………………………………………..368External cables and connectors …………………………………………………………………………..369eSATA Single Lane Cable and Connectors…………………………………………………..370eSATA Multiple-Lane Cable and Connectors ………………………………………………370Hot Plug Support…………………………………………………………………………………………372Host Bus Adapters …………………………………………………………………………………………………..373Port Multipliers ……………………………………………………………………………………………………….373Chapter 21: Hot PlugOverview………………………………………………………………………………………………………………….375Hot Plug Connector …………………………………………………………………………………………………376Cable Hot Plug Connection ………………………………………………………………………………..376Backplane Hot Plug Connector…………………………………………………………………………..377Drive Plug/Unplug Detection………………………………………………………………………………….378In-Rush Current Limiting………………………………………………………………………………………..380Asynchronous Event Notification……………………………………………………………………………380Chapter 22: Link Power ManagementOverview………………………………………………………………………………………………………………….383Configuring Link Power Management…………………………………………………………………… 384Detecting/Enabling Drive Link Power Management ………………………………………… 384Link Power Management Protocol ………………………………………………………………………….386Host Initiated Entry into Partial/Slumber ………………………………………………………….387Drive Initiated Entry into Partial/Slumber…………………………………………………………388COMWAKE Protocol …………………………………………………………………………………………389Host Initiated Wakeup…………………………………………………………………………………389Device Initiated Wakeup ……………………………………………………………………………..390Electrical Idle Conditions……………………………………………………………………………………390Idle Requirements………………………………………………………………………………………..390Special Condition for AC Coupled transmitters …………………………………………..391

ContentsxxiiChapter 23: BIST FeaturesOverview………………………………………………………………………………………………………………….393BIST FIS …………………………………………………………………………………………………………………..394BIST Format and Contents………………………………………………………………………………….394BIST Transmission/Reception ……………………………………………………………………………397Far End Node Setup …………………………………………………………………………………….397Near End Node Setup ………………………………………………………………………………….397Far End Retimed Loopback ……………………………………………………………………………………..397Far End Analog Loopback ……………………………………………………………………………………….400Far End Transmit Only…………………………………………………………………………………………….401Data Transmit Modes …………………………………………………………………………………………402Primtive Transmit Modes …………………………………………………………………………………..402Near End Analog Loopback …………………………………………………………………………………….404Test Patterns …………………………………………………………………………………………………………….405Non-Compliant Patterns…………………………………………………………………………………….405Compliant Patterns …………………………………………………………………………………………….406AppendicesAppendix A: 8b/10b Encoding Tutorial8b/10b Encoding ………………………………………………………………………………………………………409General …………………………………………………………………………………………………………………….409Purpose of Encoding a value Stream……………………………………………………………………….410Properties of 10-bit (10b) Symbols…………………………………………………………………………..411Preparing 8-bit value Notation …………………………………………………………………………..412Disparity…………………………………………………………………………………………………………….413CRD (Current Running Disparity)……………………………………………………………….4148b/10b Encoding Procedure……………………………………………………………………………………..414Example Encodings ……………………………………………………………………………………………416Example Transmission ……………………………………………………………………………………….416The Lookup Tables …………………………………………………………………………………………….417Control value Encoding ……………………………………………………………………………….420Disparity Error Checks…………………………………………………………………………………421Appendix B: ATA & SATACommandsEssential Background ………………………………………………………………………………………………423References ………………………………………………………………………………………………………….424General Characteristics of ATA Commands……………………………………………………….424Command Structure …………………………………………………………………………………….426

ContentsxxiiiNormal Outputs…………………………………………………………………………………….426Error Outputs ………………………………………………………………………………………..427Multiple Command Protocols………………………………………………………………………428Feature Sets………………………………………………………………………………………………….432Commands by Function or Feature Set…………………………………………………………………… 436Resetting and Initializing a Device……………………………………………………………………..436Hardware Reset……………………………………………………………………………………………436Software Reset ……………………………………………………………………………………………..437Device self-test …………………………………………………………………………………………….437Status presentation to host system……………………………………………………………….437Configuring a Device………………………………………………………………………………………….438IDENTIFY DEVICE – Finding Supported Features……………………………………… 438SET FEATURES – Enabling/Disabling Features …………………………………………. 438Device Configuration Overlay feature set ……………………………………………………439Host Protected Area feature set……………………………………………………………………439READ and WRITE Commands…………………………………………………………………………..43948-bit Addressing feature set ……………………………………………………………………………..440Streaming Feature feature set……………………………………………………………………………..441Tagged Queuing feature set ……………………………………………………………………………….441Power Management feature set ………………………………………………………………………….441Advanced Power Management feature set …………………………………………………………442General Purpose Logging feature set………………………………………………………………….443SMART feature set ……………………………………………………………………………………………..443Security feature set……………………………………………………………………………………………..443Packet-delivered Commands (ATAPI)……………………………………………………………………. 444SATA-only Commands……………………………………………………………………………………………445READ FPDMA QUEUED and WRITE FPDMA QUEUED…………………………………. 445READ and Write PORT MULTIPLIER Commands……………………………………………. 445Appendix C: Commands by Code…………………………………………………….. 447Appendix D: Commands by Type…………………………………………………….. 449Appendix E: Commands by Name……………………………………………………. 451Glossary …………………………………………………………………………………………………………………..453Index ………………………………………………………………………………………………………………………..459