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OCP DC-SCM 2.0 LTPI ver 0.9.pdf DC-SCM 2.0 LVDS Tunneling Protocol & Interface (LTPI) Introduction [On Demand Virtual Session].pdf 在莱迪思FPGA中实现DC-SCM.pdf

Table of Contents
1 Overview…………………………………………………………………………………………………………………………………….5
1.1 DC-SCM 2.0 LTPI Architecture ……………………………………………………………………………………………………….5
1.2 DC-SCM 2.0 LTPI Channels…………………………………………………………………………………………………………….6
1.2.1 Channels mapping to physical interfaces ……………………………………………………………………………………7
1.2.2 GPIO Channel………………………………………………………………………………………………………………………….9
1.2.3 I2C/SMBus Channel ……………………………………………………………………………………………………………….11
1.2.4 UART Channel ……………………………………………………………………………………………………………………….12
1.2.5 OEM Channels……………………………………………………………………………………………………………………….13
1.2.6 Data Channel…………………………………………………………………………………………………………………………14
2 LTPI Architecture ……………………………………………………………………………………………………………………….. 16
2.1 General Working Principle…………………………………………………………………………………………………………..17
2.2 Interfaces Tunneling Principle ……………………………………………………………………………………………………..19
2.3 LTPI Clock Topology……………………………………………………………………………………………………………………31
2.4 CRC Checksum…………………………………………………………………………………………………………………………..32
2.5 CRC Errors Handling …………………………………………………………………………………………………………………..32
2.6 8b/10b Encoding ……………………………………………………………………………………………………………………….34
2.7 LTPI Latency………………………………………………………………………………………………………………………………34
2.7.1 I2C/SMBus End-to-End Bandwidth …………………………………………………………………………………………..37
2.7.2 UART End-to-End Integrity………………………………………………………………………………………………………38
3 LTPI Frames Definition………………………………………………………………………………………………………………… 41
3.1.1 Link Detect and Link Speed Selection Frames…………………………………………………………………………….42
3.1.2 Advertise, Configure and Accept Frames…………………………………………………………………………………..44
3.1.1 LTPI Operational Frames…………………………………………………………………………………………………………47
3.2 LTPI Control and Status Registers (CSR) ………………………………………………………………………………………..50
4 LTPI Link Initialization and Operation ……………………………………………………………………………………………. 54
4.1.1 Link Training………………………………………………………………………………………………………………………….56
4.1.2 Link Configuration………………………………………………………………………………………………………………….60
4.1.3 Operational mode………………………………………………………………………………………………………………….65
4.1.4 Link Training and Configuration Example ………………………………………………………………………………….67
5 Acronyms…………………………………………………………………………………………………………………………………. 68
2 November 9, 2021
List of Figures
Figure 1 LVDS connection to SCM CPLD…………………………………………………………………………………………..5
Figure 2 Direct connection of LVDS interface to the BMC………………………………………………………………….6
Figure 3 LTPI Channels encapsulation and serialization using TDM method. ……………………………………….7
Figure 4 Example of GPIO Channel mapping to physical GPIOs ………………………………………………………….8
Figure 5 Example GPIO Channel to physical GPIOs and SGPIO interface ……………………………………………..9
Figure 6 Example of GPIO mapping to Low Latency and Normal Latency GPIOs…………………………………10
Figure 7 Example mapping of I2C Channel to physical I2C buses on HPM………………………………………….12
Figure 8 Example mapping of UART Channel to physical UART interfaces on HPM and SCM ……………….13
Figure 9 Example of OEM Channel usage for tunneling OEM-specific interface………………………………….14
Figure 10 Example Data Channel use with internal AVMM interface. ……………………………………………….15
Figure 11 Data Channel usage to access ADC registers in HPM FPGA………………………………………………..16
Figure 12 LTPI Architecture………………………………………………………………………………………………………….16
Figure 13 LTPI Block Diagram……………………………………………………………………………………………………….18
Figure 14 LTPI UART Sampling Frequency ……………………………………………………………………………………..21
Figure 15 LTPI UART Sampling distribution across LTPI Frames………………………………………………………..22
Figure 16 I2C/SMBus Relay Block Diagram…………………………………………………………………………………….23
Figure 17 Example of I2C/SMBus Channel Controller-Target connection…………………………………………..24
Figure 18 I2C/SMBus Events and clock stretching for Controller and Target side ……………………………….25
Figure 19 LTPI Clock Topology ……………………………………………………………………………………………………..31
Figure 20 LTPI Constant Latency …………………………………………………………………………………………………..35
Figure 21 LTPI Random Data Access Latency………………………………………………………………………………….35
Figure 22 LTPI Latency impact on I2C/SMBus Events………………………………………………………………………37
Figure 23 LTPI Latency impact on UART Integrity……………………………………………………………………………39
Figure 24 UART signal Jitter impact RX signal integrity ……………………………………………………………………39
Figure 25 Reduced Jitter impact by limited Data Channel Frames…………………………………………………….40
Figure 26 Example of LTPI CSR access from BMC ……………………………………………………………………………51
Figure 27 Link Training and Initialization Flow ……………………………………………………………………………….55
Figure 28 LTPI Link Detect State Frames………………………………………………………………………………………..57
Figure 29 LTPI Link Speed State Frames…………………………………………………………………………………………58
Figure 30 LTPI Advertise State Frames ………………………………………………………………………………………….61
Figure 31 LTPI Advertise State Frames ………………………………………………………………………………………….62
Figure 32 LTPI Operational State with I/O Frames Stream……………………………………………………………….65
Figure 33 Data Frames interleaving I/O Frames Stream…………………………………………………………………..66
Figure 34 Link Training and Configuration Flow ……………………………………………………………………………..67
Open Compute Project • DC-SCM Specification
http://opencompute.org 3
List of Tables
Table 1 LTPI Channels summary …………………………………………………………………………………………………….6
Table 2 Low Latency and Normal Latency GPIOs…………………………………………………………………………….10
Table 3 Example of GPIO Channel Definition for Normal Latency GPIOs from SCM perspective …………..11
Table 4 UART Signals tunneled through LTPI………………………………………………………………………………….12
Table 5 LTPI Channels working characteristics. ………………………………………………………………………………19
Table 6 LTPIO GPIO Channel Encoding…………………………………………………………………………………………..20
Table 7 UART Maximum Baud Rate example for Default IO Frame …………………………………………………..21
Table 8 UART Channels Encoding …………………………………………………………………………………………………22
Table 9 I2C/SMBus Events flow between Controller and Target LTPI I2C/SMBus Relays……………………..25
Table 10 I2C/SMBus Events Bit Encoding ………………………………………………………………………………………28
Table 11 I2C/SMBus Bit Fields Encoding in LTPI Frame ……………………………………………………………………29
Table 12 Data Bus Command encoding. ………………………………………………………………………………………..29
Table 13 Memory Read and Write operations Encoding………………………………………………………………….30
Table 14 CRC Error impact on LTPI channels ………………………………………………………………………………….32
Table 15 Frame Transfer Latencies Example ………………………………………………………………………………….36
Table 16 LTPI Latency impact on LTPI channels………………………………………………………………………………36
Table 17 I2C/SMBus Channel End-to-End Bandwidth ……………………………………………………………………..38
Table 18 Example of maximum number of consecutive Data Channel Frames…………………………………..40
Table 19 LTPI Frame types summary …………………………………………………………………………………………….41
Table 20 Link Detect and Link Speed Frame Type and Subtypes……………………………………………………….42
Table 21 Speed Capabilities Encoding …………………………………………………………………………………………..42
Table 22 Link Detect Frame …………………………………………………………………………………………………………42
Table 23 Speed Select Encoding …………………………………………………………………………………………………..43
Table 24 Link Speed Frame ………………………………………………………………………………………………………….43
Table 25 Advertise, Configure and Accept Frame Type and Subtypes……………………………………………….44
Table 26 Platform Type Encoding …………………………………………………………………………………………………44
Table 27 UART Channel Max Baud Rate Encoding…………………………………………………………………………..45
Table 28 LTPI Capabilities Encoding………………………………………………………………………………………………45
Table 29 LTPI Advertise Frame……………………………………………………………………………………………………..46
Table 30 LTPI Configure Frame …………………………………………………………………………………………………….46
Table 31 LTPI Accept Frame…………………………………………………………………………………………………………47
Table 32 LTPI Operational Frame Type and Subtypes……………………………………………………………………..48
Table 33 LTPI Default I/O Frame…………………………………………………………………………………………………..48
Table 34 LTPI Default Data Frame…………………………………………………………………………………………………49
Table 35: General Control and Status Register Map………………………………………………………………………..51
Table 36: LTPI Control and Status Registers …………………………………………………………………………………..51
Table 37 Link Detect State Overview…………………………………………………………………………………………….57
Table 38 Link Speed State Overview……………………………………………………………………………………………..58
Table 39 Speed Capabilities sent by HPM………………………………………………………………………………………59
4 November 9, 2021
Table 40 Speed Capabilities sent by SCM ………………………………………………………………………………………59
Table 41 Speed Select sent by SCM and HPM ………………………………………………………………………………..59
Table 42 Advertise State Overview……………………………………………………………………………………………….61
Table 43 Configure and Accept States Overview…………………………………………………………………………….62
Table 44 SCM Capabilities presented in Advertise Frame………………………………………………………………..63
Table 45 HPM Capabilities presented in Advertise Frame ……………………………………………………………….64
Table 46 Configuration requested in Configure Frame ……………………………………………………………………64
Table 47 Configure and Accept States Overview…………………………………………………………………………….66