UBM V1.4 协议-FPGA CPLD资料源码分享论坛-FPGA CPLD-ChipDebug

UBM V1.4 协议

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CONTENTS
1. Scope 8
2. References 9
2.1 Industry Documents 9
2.2 Sources 9
2.3 Conventions 9
3. Keywords, Acronyms, and Definitions 10
3.1 Keywords 10
3.2 Acronyms and Abbreviations 10
3.3 Definitions 11
4. General Description 12
5. Concepts 14
5.1 Host Facing Connector Requirements 14
5.2 HFC 2WIRE_RESET# signal 15
5.3 HFC PERST# signal 15
5.4 UBM FRU Sizing Considerations 15
5.5 2Wire Device Topology 16
5.6 UBM Controller Initialization Process 18
5.7 Host UBM Backplane Discovery Process 18
5.8 CPRSNT# / CHANGE_DETECT# signal 19
5.9 CHANGE_DETECT# signal interrupt handling 19
5.10 Host Facing Connector Identity 19
5.11 Host Facing Connector Starting Lane 20
5.12 Chassis Slot Mapping 20
5.13 LED State 21
5.14 LED Pattern Behavior 22
5.15 Drive Activity Behavior 22
5.16 PCIe Clock Routing and PCIe Reset Control Management 22
5.17 DFC Status and Control Descriptor 26
5.18 Bifurcation Port 26
5.19 UBM Port Route Information Descriptors 27
5.20 UBM Controller Operational State 28
5.21 UBM Controller Image Update 28
6. UBM FRU 29
6.1 UBM FRU 2Wire Protocol 30
6.2 IPMI Defined Data 30
6.3 MultiRecords 30
6.3.1 UBM Overview Area 31
6.3.1.1 Header 31
6.3.1.2 Data 31
6.3.1.2.1 Data Byte 0 Definition 31
6.3.1.2.2 Data Byte 1 Definition 32
6.3.1.2.3 Data Byte 2 Definition 32
6.3.1.2.4 Data Byte 3 and Data Byte 4 Definition 32
6.3.1.2.5 Data Byte 5 Definition 32
6.3.1.2.6 Data Byte 6 Definition 32
6.3.1.2.7 Data Byte 7 Definition 32
6.3.1.2.8 Data Byte 8 Definition 33
6.3.1.2.9 Data Byte 9 Definition 33
6.3.1.2.10 Data Byte 10 Definition 33
6.3.2 UBM Port Route Information Area 34
PUBLISHED SFF-TA-1005 Rev 1.4
Universal Backplane Management (UBM) Page 5
Copyright © 2021 SNIA. All rights reserved.
6.3.2.1 Header 34
6.3.2.2 Data 35
6.3.2.2.1 Data Byte 0 Definition 35
6.3.2.2.2 Data Byte 1 Definition 35
6.3.2.2.3 Data Byte 2 Definition 36
6.3.2.2.4 Data Byte 3 Definition 36
6.3.2.2.5 Data Byte 4 Definition 37
6.3.2.2.6 Data Byte 5 Definition 37
6.3.2.2.7 Data Byte 6 Definition 37
7. UBM Controller 38
7.1 2Wire Protocol 38
7.2 UBM Controller Commands 40
7.2.1 Operational State Command 41
7.2.2 Last Command Status Command 41
7.2.3 Silicon Identity and Version Command 42
7.2.4 Programmable Update Mode Capabilities Command 43
7.2.5 Enter Programmable Update Mode Command (Optional) 43
7.2.6 Programmable Mode Data Transfer Command (Optional) 44
7.2.6.1 2 Wire Variable Length Transactions 45
7.2.6.2 Get Non-Volatile Storage Geometry Subcommand 46
7.2.6.3 Erase Subcommand 47
7.2.6.4 Erase Status Subcommand 48
7.2.6.5 Program Subcommand 49
7.2.6.6 Program Status Subcommand 50
7.2.6.7 Verify Subcommand 50
7.2.6.8 Verify Status Subcommand 51
7.2.6.9 Verify Image Subcommand 52
7.2.6.10 Verify Image Status Subcommand 52
7.2.6.11 Set Active Image Subcommand 53
7.2.6.12 Active Image Status Subcommand 53
7.2.7 Exit Programmable Update Mode Command (Optional) 54
7.2.8 Host Facing Connector Info Command 54
7.2.9 Backplane Info Command 55
7.2.10 Starting Slot Command 55
7.2.11 Capabilities Command 55
7.2.12 Features Command 57
7.2.13 Change Count Command 59
7.2.14 DFC Status and Control Descriptor Index Command 60
7.2.15 DFC Status and Control Descriptor Command 60
Appendix A. (Informative) Host Facing Connector Sideband Signal Assignments 62
A.1 Host Facing Connector Sideband Signal Assignments 62
Appendix B. (Informative) Backplane Examples 63
B.1. Backplane Routing 63
B.2. Adapters cabled to the Backplane 64
B.3. PCIe Switch on the Backplane 67
B.4. SAS Expander on the Backplane 68
B.5. Multiple Backplanes in the Chassis 68
Appendix C. (Informative) Host Considerations 71
PUBLISHED SFF-TA-1005 Rev 1.4
Universal Backplane Management (UBM) Page 6
Copyright © 2021 SNIA. All rights reserved.
FIGURES
Figure 4-1 UBM Backplane Overview 12
Figure 4-2 UBM System Deployment view 13
Figure 5-1 2Wire Device Arrangement with DFC 2Wire behind Mux 16
Figure 5-2 2Wire Device Arrangement with UBM Controllers and DFC 2Wire behind Mux 17
Figure 5-3 Example of Multiple Backplanes Managed by One Managed Resource 21
Figure 5-4 Example of Multiple Backplanes Managed by Two Separate Managed Resources 21
Figure 6-1 UBM FRU Format 29
Figure 6-2 UBM FRU 2Wire Read Transaction 30
Figure 6-3 UBM FRU 2Wire Write Transaction 30
Figure 7-1 UBM Controller Write Transaction 38
Figure 7-2 UBM Controller Read Transaction 38
Figure 7-3 UBM Controller PMDT Write Transaction 45
Figure 7-4 UBM Controller PMDT Read Transaction 45
Figure 7-5 Non-Volatile Storage Geometry Diagram 46
Figure B-1 Multiple DFC Routing Backplane Example 63
Figure B-2 PCIe Passthrough Adapter Cabled to the Backplane Example 64
Figure B-3 PCIe Switch Adapter Cabled to the Backplane Example 65
Figure B-4 Host Bus Adapter Cabled to the Backplane Example 66
Figure B-5 PCIe Switch on the Backplane Example 67
Figure B-6 PCIe Switch on the Backplane with Multiple Connectors 68
Figure B-7 Two Identical Backplanes Example 69
TABLES
Table 5-1 Host Facing Connector Sideband Signal Requirements 14
Table 5-2 Host And UBM Controller 2WIRE_RESET# Timing 15
Table 5-3 UBM FRU Memory Size Considerations 15
Table 5-4 HFC Starting Lane Example of 2×2 DFC to 1 HFC 20
Table 5-5 Access Map to Find Actual Slot Location 20
Table 5-6 PCIe Clock Routing And PCIe Reset Control Management (No DFC PERST# Management Override) 24
Table 5-7 PCIe Clock Routing And PCIe Reset Control Management (DFC PERST# Management Override Set
to 1h and override supported) 25
Table 5-8 PCIe Clock Routing and PCIe Reset Control Management (DFC PERST# Management set to 2h and
override supported) 26
Table 5-9 SFF-8639 Connector Port Usages 27
Table 5-10 SFF-TA-1001 Connector Port Usages 27
Table 6-1 UBM FRU 2Wire Transaction Legend 30
Table 6-2 UBM Overview Area 31
Table 6-3 UBM Overview Area: Data Byte 0 Definition 31
Table 6-4 UBM Overview Area: Data Byte 1 Definition 32
Table 6-5 UBM Overview Area: Data Byte 2 Definition 32
Table 6-6 UBM Overview Area: Data Byte 5 Definition 32
Table 6-7 UBM Overview Area: Data Byte 6 Definition 32
Table 6-8 UBM Overview Area: Data Byte 7 Definition 32
Table 6-9 UBM Overview Area: Data Byte 8 Definition 33
Table 6-10 UBM Overview Area: Data Byte 9 Definition 33
Table 6-11 UBM Port Route Information Area 34
Table 6-12 UBM Port Route Information Descriptor 35
Table 6-13 Port Route Information: Data Byte 0 Definition 35
Table 6-14 Port Route Information: Data Byte 1 Definition 35
Table 6-15 Port Route Information: Data Byte 2 Definition 36
Table 6-16 Port Route Information: Data Byte 3 Definition 36
Table 6-17 Port Route Information: Data Byte 4 Definition 37
Table 6-18 Port Route Information: Data Byte 5 Definition 37
Table 6-19 Port Route Information: Data Byte 6 Definition 37
Table 7-1 UBM Controller 2wire Transaction Legend 38
PUBLISHED SFF-TA-1005 Rev 1.4
Universal Backplane Management (UBM) Page 7
Copyright © 2021 SNIA. All rights reserved.
Table 7-2 UBM Controller Successful Read Transaction Sequence 39
Table 7-3 UBM Controller Successful Write Transaction Sequence 39
Table 7-4 UBM Controller Invalid Write Transaction Sequence 39
Table 7-5 UBM Controller Invalid Read Transaction Sequence 40
Table 7-6 UBM Controller Command Set 40
Table 7-7 Operational State Command 41
Table 7-8 Operational State Command Descriptions 41
Table 7-9 Last Command Status Command 41
Table 7-10 Last Command Status Descriptions 41
Table 7-11 Silicon Identity and Version Command 42
Table 7-12 UBM Specification Version (Examples) 42
Table 7-13 Programming Update Mode Capabilities Command 43
Table 7-14 Programming Update Mode Capabilities: Data Byte 0 Definition 43
Table 7-15 Enter Programing Update Mode Command 43
Table 7-16 PMDT Write Format 44
Table 7-17 Programmable Mode Subcommands 44
Table 7-18 PMDT Read Format 45
Table 7-19 Programmable Mode Status 45
Table 7-20 PMDT Write Format for the Get Non-Volatile Storage Geometry Subcommand 46
Table 7-21 PMDT Read Format for the Get Non-Volatile Storage Geometry Subcommand 47
Table 7-22 PMDT Write Format for the Erase Subcommand 47
Table 7-23 PMDT Write Format for the Erase Status Subcommand 48
Table 7-24 PMDT Read Format for the Erase Status Subcommand 48
Table 7-25 PMDT Write Format for the Program Subcommand 49
Table 7-26 PMDT Write Format for the Program Status Subcommand 50
Table 7-27 PMDT Read Format for the Program Status Subcommand 50
Table 7-28 PMDT Write Format for the Verify Subcommand 50
Table 7-29 PMDT Write Format for the Verify Status Subcommand 51
Table 7-30 PMDT Read Format for the Verify Status Subcommand 51
Table 7-31 PMDT Write Format for the Verify Image Subcommand 52
Table 7-32 PMDT Write Format for the Verify Image Status Subcommand 52
Table 7-33 PMDT Read Format for the Verify Image Status Subcommand 52
Table 7-34 PMDT Write Format for the Set Active Image Subcommand 53
Table 7-35 PMDT Write Format for the Active Image Status Subcommand 53
Table 7-36 PMDT Read Format for the Active Image Status Subcommand 53
Table 7-37 Exit Programmable Update Mode Command 54
Table 7-38 Host Facing Connector Info Command 54
Table 7-39 Host Facing Connector Info: Data Byte 0 Definition 54
Table 7-40 Backplane Info Command 55
Table 7-41 Backplane Info: Data Byte 0 Definition 55
Table 7-42 Starting Slot Command 55
Table 7-43 Capabilities Command 55
Table 7-44 Capabilities Command: Data Byte 0 Definition 56
Table 7-45 Capabilities Command: Data Byte 1 Definition 57
Table 7-46 Features Command 57
Table 7-47 Features Command: Data Byte 0 Definition 58
Table 7-48 Features Command: Data Byte 1 Definition 58
Table 7-49 Change Count Command 59
Table 7-50 DFC Status and Control Descriptor Index Command 60
Table 7-51 DFC Status and Control Descriptor Command 60
Table 7-52 DFC Status and Control Descriptor: Data Byte 0 Definition 61
Table A-1 SFF-9402 Sideband Signal Assignments 62

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