eSPI V1.0 协议文档

Contents
1 Glossary …………………………………………………………………………………………… 8
2 Introduction ………………………………………………………………………………………. 9
2.1 Requirements …………………………………………………………………………. 12
3 Architecture Overview ………………………………………………………………………… 14
3.1 System Topology……………………………………………………………………… 14
3.2 Architecture Descriptions……………………………………………………………. 18
3.3 Pin Descriptions ………………………………………………………………………. 22
4 Bus Protocol…………………………………………………………………………………….. 24
4.1 Basic Protocol …………………………………………………………………………. 24
4.2 Command Phase ……………………………………………………………………… 28
4.3 Turn-Around (TAR) …………………………………………………………………… 33
4.4 Response Phase ………………………………………………………………………. 34
4.4.1 Response …………………………………………………………………… 34
4.4.2 Status ………………………………………………………………………. 36
4.5 Alert Phase…………………………………………………………………………….. 39
4.6 Get Status Command………………………………………………………………… 42
4.7 Get Configuration and Set Configuration Command ……………………………. 44
4.8 Non-Posted Transaction……………………………………………………………… 45
4.9 Posted Transaction …………………………………………………………………… 49
4.10 WAIT STATE …………………………………………………………………………… 51
5 Transaction Layer ……………………………………………………………………………… 53
5.1 Cycle Types and Packet Format ……………………………………………………. 53
5.1.1 Cycle Types………………………………………………………………… 54
5.1.2 Tag ………………………………………………………………………….. 57
5.1.3 Length………………………………………………………………………. 57
5.1.4 Address …………………………………………………………………….. 58
5.1.5 Data…………………………………………………………………………. 59
5.2 Channels……………………………………………………………………………….. 59
5.2.1 Peripheral Channel ……………………………………………………….. 59
5.2.2 Virtual Wires Channel…………………………………………………….. 66
5.2.3 OOB (Tunneled SMBus) Message Channel ……………………………. 83
5.2.4 Run-time Flash Access Channel ………………………………………… 85
5.3 Slave Buffer Management…………………………………………………………… 89
5.4 Transaction Ordering Rule ………………………………………………………….. 91
5.5 Zero Length Read and Write ……………………………………………………….. 92
6 Link Layer……………………………………………………………………………………….. 93
6.1 Single I/O, Dual I/O and Quad I/O Modes ……………………………………….. 93
4 327432-004
6.2 Cyclic Redundancy Check (CRC) …………………………………………………… 98
7 Slave Registers…………………………………………………………………………………100
7.1 Status Register ……………………………………………………………………….100
7.2 Capabilities and Configuration Registers …………………………………………101
8 Operating Specification ……………………………………………………………………….114
8.1 Electrical Specification……………………………………………………………….114
8.2 Timing Parameters …………………………………………………………………..115
9 System Architecture …………………………………………………………………………..118
9.1 Interrupts ……………………………………………………………………………..118
9.2 Error Detection and Handling ………………………………………………………118
9.2.1 Slave’s Detected Errors ………………………………………………….119
9.2.2 Master’s Detected Errors ………………………………………………..127
9.3 Reset……………………………………………………………………………………131
9.3.1 eSPI Reset# ……………………………………………………………….131
9.3.2 In-band RESET Command……………………………………………….131
9.4 Power Management Event (PME) ………………………………………………….132
9.5 Power Sequencing & Initialization …………………………………………………132
9.5.1 Exit from G3……………………………………………………………….133
Figures
Figure 1: EC/BMC/SIO Communication over LPC…………………………………………. 10
Figure 2: EC/BMC/SIO Communication over eSPI ……………………………………….. 11
Figure 3: Example of LPC bus and Additional eSPI bus behind the eSPI ……………… 12
Figure 4: Single Master-Single Slave with eSPI Reset# from Slave to Master ………. 14
Figure 5: Single Master-Single Slave with eSPI Reset# from Master to Slave ………. 15
Figure 6: Single Master-Multiple Slaves with Two eSPI Reset#………………………… 16
Figure 7: Single Master-Single Slave (Multiple Channels) ………………………………. 18
Figure 8: Single Master-Multiple Slaves ……………………………………………………. 20
Figure 9: EC/BMC/SIO Communication Over eSPI Channels……………………………. 21
Figure 10: Basic eSPI Protocol ………………………………………………………………. 24
Figure 11: Slave Triggered Transaction (Single Master-Slave) ………………………… 25
Figure 12: Slave Triggered Transaction (Multiple Slave)………………………………… 27
Figure 13: Command Opcode ……………………………………………………………….. 28
Figure 14: Turn-Around Time (TAR = 2 clock) ……………………………………………. 33
Figure 15: Response Field ……………………………………………………………………. 34
Figure 16: Slave’s Status Register Definition ……………………………………………… 36
Figure 17: Flow Diagram for a Slave to Master Peripheral Posted Write ……………… 40
Figure 18: Flow Diagram for a Back-to-back Slave to Master Peripheral Posted Write40
327432-004 5
Figure 19: Flow Diagram for a Slave to Master Peripheral Posted Write passes Nonposted………………………………………………………………………………………. 41
Figure 20: GET_STATUS Command…………………………………………………………. 42
Figure 21: GET_STATUS Command (with Response Modifier) …………………………. 43
Figure 22: GET_CONFIGURATION Command……………………………………………… 44
Figure 23: SET_CONFIGURATION Command ……………………………………………… 44
Figure 24: Connected Master Initiated Non-Posted Transaction ……………………….. 45
Figure 25: Deferred Master Initiated Non-Posted Transaction …………………………. 46
Figure 26: Master Initiated Short Non-Posted Transaction……………………………… 47
Figure 27: Slave Initiated Non-Posted Transaction ………………………………………. 48
Figure 28: Master Initiated Posted Transaction …………………………………………… 49
Figure 29: Master Initiated Short Posted Transaction……………………………………. 49
Figure 30: Slave Initiated Posted Transaction…………………………………………….. 50
Figure 31: Pipelined Back-to-Back Bus Mastering Posted Write Transactions ……….. 51
Figure 32: Master Initiated Non-Posted Transaction Responded with WAIT STATE…. 52
Figure 33: General eSPI Packet Format ……………………………………………………. 53
Figure 34: Peripheral Memory Write Packet Format……………………………………… 60
Figure 35: Short Peripheral Memory or Short I/O Write Packet Format (Master
Initiated only) …………………………………………………………………………….. 61
Figure 36: Peripheral Memory Read Packet Format ……………………………………… 61
Figure 37: Short Peripheral Memory or Short I/O Read Packet Format (Master Initiated
only) 62
Figure 38: Peripheral Message Packet Format ……………………………………………. 62
Figure 39: Peripheral Memory or I/O Completion With and Without Data Packet
Format……………………………………………………………………………………… 63
Figure 40: LTR Message Format …………………………………………………………….. 65
Figure 41: Virtual Wire Packet Format……………………………………………………… 67
Figure 42: Virtual Wires at the Receiver …………………………………………………… 68
Figure 43: Virtual Wires with Sequence Communicated…………………………………. 79
Figure 44: Edge-triggered Interrupt through Virtual Wire ………………………………. 82
Figure 45: OOB (Tunneled SMBus) Message Packet Format……………………………. 83
Figure 46: OOB MCTP Packet………………………………………………………………… 84
Figure 47: OOB Generic SMBus Block Write Format……………………………………… 85
Figure 48: Flash Access Request Packet Format………………………………………….. 86
Figure 49: Flash Access Completion Packet Format ……………………………………… 86
Figure 50: Independent Flash SPI and eSPI Interface …………………………………… 87
Figure 51: Shared SPI and eSPI Interface…………………………………………………. 87
Figure 52: eSPI Slave Buffer Design (Conceptual)……………………………………….. 91
Figure 53: Byte Ordering on the eSPI Bus…………………………………………………. 94
Figure 54: Single I/O Mode ………………………………………………………………….. 95
Figure 55: Dual I/O Mode…………………………………………………………………….. 96
Figure 56: Quad I/O Mode……………………………………………………………………. 97
Figure 57: CRC Polynomial Representation ……………………………………………….. 98
Figure 58: Input Timing Diagram …………………………………………………………..116
Figure 59: Output Timing Diagram …………………………………………………………117
Figure 60: Transaction with FATAL Error Response………………………………………125
6 327432-004
Figure 61: Transaction with Non-FATAL Error Response ………………………………..125
Figure 62: Unexpected Chip Select# Deassertion………………………………………..126
Figure 63: In-band RESET Command ………………………………………………………132
Tables
Table 1: Table of Glossary……………………………………………………………………… 8
Table 2: eSPI Pin List …………………………………………………………………………. 22
Table 3: Command Opcode Encodings……………………………………………………… 28
Table 4: Response Field Encodings …………………………………………………………. 35
Table 5: Status Field Encodings……………………………………………………………… 37
Table 6: Cycle Types ………………………………………………………………………….. 54
Table 7: Message Codes………………………………………………………………………. 63
Table 8: LTR Message Field Description ……………………………………………………. 65
Table 9: Virtual Wire Index Definition………………………………………………………. 69
Table 10: System Event Virtual Wires for Index=2………………………………………. 72
Table 11: System Event Virtual Wires for Index=3………………………………………. 73
Table 12: System Event Virtual Wires for Index=4………………………………………. 74
Table 13: System Event Virtual Wires for Index=5………………………………………. 75
Table 14: System Event Virtual Wires for Index=6………………………………………. 76
Table 15: System Event Virtual Wires for Index=7………………………………………. 78
Table 16: Interrupt Event (IRQ) Virtual Wire Generation……………………………….. 80
Table 17: CRC Byte with Input Data D7:D0 (⊕ denotes logical XOR) ………………… 99
Table 18: Register Attribute Description …………………………………………………..100
Table 19: Register Default Values Encoding Description ………………………………..100
Table 20: Slave Registers…………………………………………………………………….101
Table 21: Electrical Specification ……………………………………………………………114
Table 22: AC Timing Specification…………………………………………………………..115
Table 23: Slave’s Detected Errors…………………………………………………………..119
Table 24: Master’s Detected Errors …………………………………………………………127