今天主要介绍AXI的开源项目
1Alexforencich的AXI
介绍
主要包含AXI-lite,AXI,包含crossbar以及interconnect等,完成度非常高,语言为Verilog。主要文件以及仓库地址如下:
rtl/arbiter.v : Parametrizable arbiter rtl/axi_adapter.v : AXI lite width converter rtl/axi_adapter_rd.v : AXI lite width converter (read) rtl/axi_adapter_wr.v : AXI lite width converter (write) rtl/axi_axil_adapter.v : AXI to AXI lite converter rtl/axi_axil_adapter_rd.v : AXI to AXI lite converter (read) rtl/axi_axil_adapter_wr.v : AXI to AXI lite converter (write) rtl/axi_cdma.v : AXI central DMA engine rtl/axi_cdma_desc_mux.v : AXI CDMA descriptor mux rtl/axi_crossbar.v : AXI nonblocking crossbar interconnect rtl/axi_crossbar_addr.v : AXI crossbar address module rtl/axi_crossbar_rd.v : AXI crossbar interconnect (read) rtl/axi_crossbar_wr.v : AXI crossbar interconnect (write) rtl/axi_dma.v : AXI DMA engine rtl/axi_dma_desc_mux.v : AXI DMA descriptor mux rtl/axi_dma_rd.v : AXI DMA engine (read) rtl/axi_dma_wr.v : AXI DMA engine (write) rtl/axi_dp_ram.v : AXI dual-port RAM rtl/axi_fifo.v : AXI FIFO rtl/axi_fifo_rd.v : AXI FIFO (read) rtl/axi_fifo_wr.v : AXI FIFO (write) rtl/axi_interconnect.v : AXI shared interconnect rtl/axi_ram.v : AXI RAM rtl/axi_ram_rd_if.v : AXI RAM read interface rtl/axi_ram_wr_if.v : AXI RAM write interface rtl/axi_ram_wr_rd_if.v : AXI RAM read/write interface rtl/axi_register.v : AXI register rtl/axi_register_rd.v : AXI register (read) rtl/axi_register_wr.v : AXI register (write) rtl/axil_adapter.v : AXI lite width converter rtl/axil_adapter_rd.v : AXI lite width converter (read) rtl/axil_adapter_wr.v : AXI lite width converter (write) rtl/axil_cdc.v : AXI lite CDC rtl/axil_cdc_rd.v : AXI lite CDC (read) rtl/axil_cdc_wr.v : AXI lite CDC (write) rtl/axil_crossbar.v : AXI lite nonblocking crossbar interconnect rtl/axil_crossbar_addr.v : AXI lite crossbar address module rtl/axil_crossbar_rd.v : AXI lite crossbar interconnect (read) rtl/axil_crossbar_wr.v : AXI lite crossbar interconnect (write) rtl/axil_interconnect.v : AXI lite shared interconnect rtl/axil_ram.v : AXI lite RAM rtl/axil_reg_if.v : AXI lite register interface rtl/axil_reg_if_rd.v : AXI lite register interface (read) rtl/axil_reg_if_wr.v : AXI lite register interface (write) rtl/axil_register.v : AXI lite register rtl/axil_register_rd.v : AXI lite register (read) rtl/axil_register_wr.v : AXI lite register (write) rtl/priority_encoder.v : Parametrizable priority encoder
仓库地址:
https://github.com/alexforencich/verilog-axi/tree/master/rtl
2Alexforencich的AXI-S
同样来自Alexforencich,代码为AXIS,完成度相当高,语言为Verilog,不错的参考代码。
arbiter.v : General-purpose parametrizable arbiter axis_adapter.v : Parametrizable bus width adapter axis_arb_mux.v : Parametrizable arbitrated multiplexer axis_async_fifo.v : Parametrizable asynchronous FIFO axis_async_fifo_adapter.v : FIFO/width adapter wrapper axis_broadcast.v : AXI stream broadcaster axis_cobs_decode.v : COBS decoder axis_cobs_encode.v : COBS encoder axis_crosspoint.v : Parametrizable crosspoint switch axis_demux.v : Parametrizable demultiplexer axis_fifo.v : Parametrizable synchronous FIFO axis_fifo_adapter.v : FIFO/width adapter wrapper axis_frame_join.v : Parametrizable frame joiner axis_frame_length_adjust.v : Frame length adjuster axis_frame_length_adjust_fifo.v : Frame length adjuster with FIFO axis_ll_bridge.v : AXI stream to LocalLink bridge axis_mux.v : Multiplexer generator axis_pipeline_fifo.v : AXI stream register pipeline with FIFO axis_pipeline_register.v : AXI stream register pipeline axis_ram_switch.v : AXI stream RAM switch axis_rate_limit.v : Fractional rate limiter axis_register.v : AXI Stream register axis_srl_fifo.v : SRL-based FIFO axis_srl_register.v : SRL-based register axis_switch.v : Parametrizable AXI stream switch axis_stat_counter.v : Statistics counter axis_tap.v : AXI stream tap ll_axis_bridge.v : LocalLink to AXI stream bridge priority_encoder.v : Parametrizable priority encoder
仓库地址:
https://github.com/alexforencich/verilog-axis
3Pulp-platform的AXI
介绍
完成度比较高,包含AXI Crossbar,AXI-lite,AXI-lite转AXI以及apb,语言为SystemVerilog,文档比较详细。
仓库地址:
https://github.com/pulp-platform/axi
4TVIP的AXI
介绍
完成度比较高,支持AXI4和AXI-lite,语言为SystemVerilog,支持Synopsys VCS和Cadence Xcelium仿真工具,具体可以参考官方。
仓库地址
https://github.com/taichi-ishitani/tvip-axi
5总结
对于优质开源代码系列,亦安每隔一段时间就会更新一次,除了Github以外,大家也可以到OpenCores上面找,对于新学者来讲,还是有相当的代码是值参考的。
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