AXI-Stream的IP核
今天带来的开源IP是AXI-Stream
语言：Verilog
来源：
https://github.com/alexforencich/verilog-axis/
介绍：AXI Stream 总线组件的集合。大多数组件的接口宽度都可以完全参数化。包括带有智能总线协同仿真端点的完整 MyHDL 测试平台。
特点：
- AXI stream bus width adapter
- AXI stream synchronous FIFO
- AXI stream asynchronous FIFO
- AXI stream synchronous frame FIFO
- AXI stream asynchronous frame FIFO
- AXI stream/LocalLink bridge
- AXI stream rate limiter
- AXI stream statistics collection
通用信号：
tdata : Data (width generally DATA_WIDTH) tkeep : Data word valid (width generally KEEP_WIDTH) tvalid : Data valid tready : Sink ready tlast : End-of-frame tid : Identifier tag (width generally ID_WIDTH) tdest : Destination tag (width generally DEST_WIDTH) tuser : User sideband signals (width generally USER_WIDTH)
通用参数：
DATA_WIDTH : width of tdata signalKEEP_ENABLE : enable tkeep signal (default DATA_WIDTH>8)KEEP_WIDTH : width of tkeep signal (default DATA_WIDTH/8)LAST_ENABLE : enable tlast signalID_ENABLE : enable tid signalID_WIDTH : width of tid signalDEST_ENABLE : enable tdest signalDEST_WIDTH : width of tdest signalUSER_ENABLE : enable tuser signalUSER_WIDTH : width of tuser signalUSER_BAD_FRAME_VALUE : value of tuser indicating bad frameUSER_BAD_FRAME_MASK : bitmask for tuser bad frame indication
源文件：
arbiter.v : General-purpose parametrizable arbiteraxis_adapter.v : Parametrizable bus width adapteraxis_arb_mux.v : Parametrizable arbitrated multiplexeraxis_async_fifo.v : Parametrizable asynchronous FIFOaxis_async_fifo_adapter.v : FIFO/width adapter wrapperaxis_broadcast.v : AXI stream broadcasteraxis_cobs_decode.v : COBS decoderaxis_cobs_encode.v : COBS encoderaxis_crosspoint.v : Parametrizable crosspoint switchaxis_demux.v : Parametrizable demultiplexeraxis_fifo.v : Parametrizable synchronous FIFOaxis_fifo_adapter.v : FIFO/width adapter wrapperaxis_frame_join.v : Parametrizable frame joineraxis_frame_length_adjust.v : Frame length adjusteraxis_frame_length_adjust_fifo.v : Frame length adjuster with FIFOaxis_ll_bridge.v : AXI stream to LocalLink bridgeaxis_mux.v : Multiplexer generatoraxis_ram_switch.v : AXI stream RAM switchaxis_rate_limit.v : Fractional rate limiteraxis_register.v : AXI Stream registeraxis_srl_fifo.v : SRL-based FIFOaxis_srl_register.v : SRL-based registeraxis_switch.v : Parametrizable AXI stream switchaxis_stat_counter.v : Statistics counteraxis_tap.v : AXI stream tapll_axis_bridge.v : LocalLink to AXI stream bridgepriority_encoder.v : Parametrizable priority encoder
AXI Stream 接口示例：
两个字节传输，每个字节后接收器暂停
__ __ __ __ __ __ __ __ __ clk __/ __/ __/ __/ __/ __/ __/ __/ __/ __ _____ _________________ tdata XXXXXXXXX_D0__X_D1______________XXXXXXXXXXXXXXXXXXXXXXXX _____ _________________ tkeep XXXXXXXXX_K0__X_K1______________XXXXXXXXXXXXXXXXXXXXXXXX _______________________ tvalid ________/ _______________________ ______________ _____ ___________ tready ___________/ ___________/ _________________ tlast ______________/ _______________________ tuser ________________________________________________________
两个背靠背的数据包，没有停顿
__ __ __ __ __ __ __ __ __ clk __/ __/ __/ __/ __/ __/ __/ __/ __/ __ _____ _____ _____ _____ _____ _____ tdata XXXXXXXXX_A0__X_A1__X_A2__X_B0__X_B1__X_B2__XXXXXXXXXXXX _____ _____ _____ _____ _____ _____ tkeep XXXXXXXXX_K0__X_K1__X_K2__X_K0__X_K1__X_K2__XXXXXXXXXXXX ___________________________________ tvalid ________/ ___________ ________________________________________________________ tready _____ _____ tlast ____________________/ ___________/ ___________ tuser ________________________________________________________
错误帧
__ __ __ __ __ __ clk __/ __/ __/ __/ __/ __/ __ _____ _____ _____ tdata XXXXXXXXX_A0__X_A1__X_A2__XXXXXXXXXXXX _____ _____ _____ tkeep XXXXXXXXX_K0__X_K1__X_K2__XXXXXXXXXXXX _________________ tvalid ________/ ___________ ______________________________________ tready _____ tlast ____________________/ ___________ _____ tuser ____________________/ ___________
模块功能：
略，请参看Github或者文件内。
总结：
使用语言：Verilog
IP核来源：
https://github.com/alexforencich/verilog-axis/
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