基本介绍：
千兆位和10G数据包处理（8位和64位数据路径）的以太网相关组件的集合。包括用于处理以太网帧以及IP，UDP和ARP的模块，以及用于构建完整UDP/IP堆栈的组件。包括用于千兆位和10G的MAC模块，一个10G PCS/ PMA PHY模块以及一个10G组合MAC/PCS/PMA模块。还包括带有智能总线协同仿真端点的完整MyHDL测试平台。
仅对于IP和ARP支持，请使用ip_complete（1G）或ip_complete_64（10G）。
对于UDP，IP和ARP支持，请使用udp_complete（1G）或udp_complete_64（10G）。
顶层千兆和10G MAC模块是eth_mac_ *，具有各种接口，并且带有/不带有FIFO。顶层10G PCS/PMA PHY模块为eth_phy_10g。顶层10G MAC/ PCS/PMA组合模块为eth_mac_phy_10g。
通用信号：
tdata : Data (width generally DATA_WIDTH)
tkeep : Data word valid (width generally KEEP_WIDTH, present on _64 modules)
tvalid : Data valid
tready : Sink ready
tlast : End-of-frame
tuser : Bad frame (valid with tlast & tvalid)
文件如下：
rtl/arp.v : ARP handling logic
rtl/arp_64.v : ARP handling logic (64 bit)
rtl/arp_cache.v : ARP LRU cache
rtl/arp_eth_rx.v : ARP frame receiver
rtl/arp_eth_rx_64.v : ARP frame receiver (64 bit)
rtl/arp_eth_tx.v : ARP frame transmitter
rtl/arp_eth_tx_64.v : ARP frame transmitter (64 bit)
rtl/eth_arb_mux.py : Ethernet frame arbitrated multiplexer generator
rtl/axis_eth_fcs.v : Ethernet FCS calculator
rtl/axis_eth_fcs_64.v : Ethernet FCS calculator (64 bit)
rtl/axis_eth_fcs_insert.v : Ethernet FCS inserter
rtl/axis_eth_fcs_check.v : Ethernet FCS checker
rtl/axis_gmii_rx.v : AXI stream GMII/MII receiver
rtl/axis_gmii_tx.v : AXI stream GMII/MII transmitter
rtl/axis_xgmii_rx_32.v : AXI stream XGMII receiver (32 bit)
rtl/axis_xgmii_rx_64.v : AXI stream XGMII receiver (64 bit)
rtl/axis_xgmii_tx_32.v : AXI stream XGMII transmitter (32 bit)
rtl/axis_xgmii_tx_64.v : AXI stream XGMII transmitter (64 bit)
rtl/eth_arb_mux.v : Ethernet frame arbitrated multiplexer
rtl/eth_axis_rx.v : Ethernet frame receiver
rtl/eth_axis_rx_64.v : Ethernet frame receiver (64 bit)
rtl/eth_axis_tx.v : Ethernet frame transmitter
rtl/eth_axis_tx_64.v : Ethernet frame transmitter (64 bit)
rtl/eth_demux.v : Ethernet frame demultiplexer
rtl/eth_mac_1g.v : Gigabit Ethernet GMII MAC
rtl/eth_mac_1g_fifo.v : Gigabit Ethernet GMII MAC with FIFO
rtl/eth_mac_1g_gmii.v : Tri-mode Ethernet GMII/MII MAC
rtl/eth_mac_1g_gmii_fifo.v : Tri-mode Ethernet GMII/MII MAC with FIFO
rtl/eth_mac_1g_rgmii.v : Tri-mode Ethernet RGMII MAC
rtl/eth_mac_1g_rgmii_fifo.v : Tri-mode Ethernet RGMII MAC with FIFO
rtl/eth_mac_10g.v : 10G Ethernet XGMII MAC
rtl/eth_mac_10g_fifo.v : 10G Ethernet XGMII MAC with FIFO
rtl/eth_mac_mii.v : Ethernet MII MAC
rtl/eth_mac_mii_fifo.v : Ethernet MII MAC with FIFO
rtl/eth_mac_phy_10g.v : 10G Ethernet XGMII MAC/PHY
rtl/eth_mac_phy_10g_fifo.v : 10G Ethernet XGMII MAC/PHY with FIFO
rtl/eth_mac_phy_10g_rx.v : 10G Ethernet XGMII MAC/PHY RX with FIFO
rtl/eth_mac_phy_10g_tx.v : 10G Ethernet XGMII MAC/PHY TX with FIFO
rtl/eth_mux.v : Ethernet frame multiplexer
rtl/gmii_phy_if.v : GMII PHY interface
rtl/iddr.v : Generic DDR input register
rtl/ip.v : IPv4 block
rtl/ip_64.v : IPv4 block (64 bit)
rtl/ip_arb_mux.v : IP frame arbitrated multiplexer
rtl/ip_complete.v : IPv4 stack (IP-ARP integration)
rtl/ip_complete_64.v : IPv4 stack (IP-ARP integration) (64 bit)
rtl/ip_demux.v : IP frame demultiplexer
rtl/ip_eth_rx.v : IPv4 frame receiver
rtl/ip_eth_rx_64.v : IPv4 frame receiver (64 bit)
rtl/ip_eth_tx.v : IPv4 frame transmitter
rtl/ip_eth_tx_64.v : IPv4 frame transmitter (64 bit)
rtl/ip_mux.v : IP frame multiplexer
rtl/lfsr.v : Generic LFSR/CRC module
rtl/oddr.v : Generic DDR output register
rtl/mii_phy_if.v : MII PHY interface
rtl/rgmii_phy_if.v : RGMII PHY interface
rtl/ssio_ddr_in.v : Generic source synchronous IO DDR input module
rtl/ssio_ddr_in_diff.v : Generic source synchronous IO DDR differential input module
rtl/ssio_ddr_out.v : Generic source synchronous IO DDR output module
rtl/ssio_ddr_out_diff.v : Generic source synchronous IO DDR differential output module
rtl/ssio_sdr_in.v : Generic source synchronous IO SDR input module
rtl/ssio_sdr_in_diff.v : Generic source synchronous IO SDR differential input module
rtl/ssio_sdr_out.v : Generic source synchronous IO SDR output module
rtl/ssio_sdr_out_diff.v : Generic source synchronous IO SDR differential output module
rtl/udp.v : UDP block
rtl/udp_64.v : UDP block (64 bit)
rtl/udp_arb_mux.v : UDP frame arbitrated multiplexer
rtl/udp_checksum_gen.v : UDP checksum generator
rtl/udp_checksum_gen_64.v : UDP checksum generator (64 bit)
rtl/udp_complete.v : UDP stack (IP-ARP-UDP)
rtl/udp_complete_64.v : UDP stack (IP-ARP-UDP) (64 bit)
rtl/udp_demux.v : UDP frame demultiplexer
rtl/udp_ip_rx.v : UDP frame receiver
rtl/udp_ip_rx_64.v : UDP frame receiver (64 bit)
rtl/udp_ip_tx.v : UDP frame transmitter
rtl/udp_ip_tx_64.v : UDP frame transmitter (64 bit)
rtl/udp_mux.v : UDP frame multiplexer
rtl/xgmii_baser_dec_64.v : XGMII 10GBASE-R decoder
rtl/xgmii_baser_enc_64.v : XGMII 10GBASE-R encoder
rtl/xgmii_deinterleave.v : XGMII data/control de-interleaver
rtl/xgmii_interleave.v : XGMII data/control interleaver
AXI Stream 接口示例：
与标头数据一起传输
__ __ __ __ __ __ __
clk __/ __/ __/ __/ __/ __/ __/ __
______________ ___________
hdr_ready _________________/
_____
hdr_valid ________/ _____________________________
_____
hdr_data XXXXXXXXX_HDR_XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
___________ _____ _____
tdata XXXXXXXXX_A0________X_A1__X_A2__XXXXXXXXXXXX
___________ _____ _____
tkeep XXXXXXXXX_K0________X_K1__X_K2__XXXXXXXXXXXX
_______________________
tvalid ________/ ___________
_________________
tready ______________/ ___________
_____
tlast __________________________/ ___________
tuser ____________________________________________
两个字节的传输，每个字节后都有接收器暂停
__ __ __ __ __ __ __ __ __
clk __/ __/ __/ __/ __/ __/ __/ __/ __/ __
_____ _________________
tdata XXXXXXXXX_D0__X_D1______________XXXXXXXXXXXXXXXXXXXXXXXX
_____ _________________
tkeep XXXXXXXXX_K0__X_K1______________XXXXXXXXXXXXXXXXXXXXXXXX
_______________________
tvalid ________/ _______________________
______________ _____ ___________
tready ___________/ ___________/
_________________
tlast ______________/ _______________________
tuser ________________________________________________________
两个背对背数据包，无暂停
__ __ __ __ __ __ __ __ __
clk __/ __/ __/ __/ __/ __/ __/ __/ __/ __
_____ _____ _____ _____ _____ _____
tdata XXXXXXXXX_A0__X_A1__X_A2__X_B0__X_B1__X_B2__XXXXXXXXXXXX
_____ _____ _____ _____ _____ _____
tkeep XXXXXXXXX_K0__X_K1__X_K2__X_K0__X_K1__X_K2__XXXXXXXXXXXX
___________________________________
tvalid ________/ ___________
________________________________________________________
tready
_____ _____
tlast ____________________/ ___________/ ___________
tuser ________________________________________________________
测试文件：
tb/arp_ep.py : MyHDL ARP frame endpoints
tb/axis_ep.py : MyHDL AXI Stream endpoints
tb/baser_serdes.py : MyHDL 10GBASE-R SERDES endpoints
tb/eth_ep.py : MyHDL Ethernet frame endpoints
tb/gmii_ep.py : MyHDL GMII endpoints
tb/ip_ep.py : MyHDL IP frame endpoints
tb/mii_ep.py : MyHDL MII endpoints
tb/rgmii_ep.py : MyHDL RGMII endpoints
tb/udp_ep.py : MyHDL UDP frame endpoints
tb/xgmii_ep.py : MyHDL XGMII endpoints
测试：
运行包含的测试平台需要使用cocotb，cocotbext-axi，cocotbext-eth和Icarus Verilog。可以直接使用pytest（需要cocotb-test），通过tox或通过cocotb makefile进行pytest来运行测试平台。
模块功能：
略，参看文件，压缩包有各种芯片的工程示例，也有原资料的原文地址。
获取代码：
