国外FPGA数字电路设计书籍第4期

本书重点介绍数字电路设计的开发、验证和综合。Verilog 语言以集成但选择性的方式引入，仅在支持设计示例时才需要（包括其他语言详细信息的附录）。它解决了计算机系统、数字信号处理、图像处理和其他应用中使用的几个重要电路的设计。

图1 Advanced Digital Design With the Verilog HDL

目录如下：

1 Introduction to Digital Design Methodology 1

1.1 Design Methodology–An Introduction

1.1.1 Design Specification

1.1.2 Design Partition

1.1.3 Design Entry

1.1.4 Simulation and Functional Verification

1.1.5 Design Integration and Verification

1.1.6 Presynthesis Sign-Off

1.1.7 Gate-Level Synthesis and Technology Mapping

1.1.8 Postsynthesis Design Validation

1.1.9 Postsynthesis Timing Verification

1.1.10 Test Generation and Fault Simulation

1.1.11 Placement and Routing

1.1.12 Physical and Electrical Design Rule Checks

1.1.13 Parasitic Extraction

1.1.14 Design Sign-Off

1.2 IC Technology Options

1.3 Overview

References

2 Review of Combinational Logic Design 13

2.1 Combinational Logic and Boolean Algebra

2.1.1 ASIC Library Cells

2.1.2 Boolean Algebra

2.1.3 DeMorgan’s Laws

2.2 Theorems for Boolean Algebraic Minimization

2.3 Representation of Combinational Logic

2.3.1 Sum-of-Products Representation

2.3.2 Product-of-Sums Representation

2.4 Simplification of Boolean Expressions

2.4.1 Simplification with Exclusive-Or

2.4.2 Karnaugh Maps (SOP Form)

2.4.3 Karnaugh Maps (POS Form)

2.4.4 Karnaugh Maps and Don’t-Cares

2.4.5 Extended Karnaugh Maps

2.5 Glitches and Hazards

2.5.1 Elimination of Static Hazards (SOP Form)

2.5.2 Summary: Elimination of Static Hazards in Two-Level Circuits

2.5.3 Static Hazards in Multilevel Circuits

2.5.4 Summary: Elimination of Static Hazards in Multilevel Circuits

2.5.5 Dynamic Hazards

2.6 Building Blocks for Logic Design

2.6.1 NAND—NOR Structures

2.6.2 Multiplexers

2.6.3 Demultiplexers

2.6.4 Encoders

2.6.5 Priority Encoder

2.6.6 Decoder

2.6.7 Priority Decoder

References

Problems

3 Fundamentals of Sequential Logic Design 69

3.1 Storage Elements

3.1.1 Latches

3.1.2 Transparent Latches

3.2 Flip-Flops

3.2.1 D-Type Flip-Flop

3.2.2 Master—Slave Flip-Flop

3.2.3 J-K Flip-Flops

3.2.4 T Flip-Flop

3.3 Busses and Three-State Devices

3.4 Design of Sequential Machines

3.5 State-Transition Graphs

3.6 Design Example: BCD to Excess-3 Code Converter

3.7 Serial-Line Code Converter for Data Transmission

3.7.1 Design Example: A Mealy-Type FSM for Serial Line-Code Conversion

3.7.2 Design Example: A Moore-Type FSM for Serial Line-Code Conversion

3.8 State Reduction and Equivalent States

References

Problems

4 Introduction to Logic Design with Verilog 103

4.1 Structural Models of Combinational Logic

4.1.1 Verilog Primitives and Design Encapsulation

4.1.2 Verilog Structural Models

4.1.3 Module Ports

4.1.4 Some Language Rules

4.1.5 Top-Down Design and Nested Modules

4.1.6 Design Hierarchy and Source-Code Organization

4.1.7 Vectors in Verilog

4.1.8 Structural Connectivity

4.2 Logic System, Design Verification, and Test Methodology

4.2.1 Four-Value Logic and Signal Resolution in Verilog

4.2.2 Test Methodology

4.2.3 Signal Generators for Testbenches

4.2.4 Event-Driven Simulation

4.2.5 Testbench Template

4.2.6 Sized Numbers

4.3 Propagation Delay

4.3.1 Inertial Delay

4.3.2 Transport Delay

4.4 Truth Table Models of Combinational and Sequential Logic with Verilog

References

Problems

5 Logic Design with Behavioral Models of Combinational

and Sequential Logic 141

5.1 Behavioral Modeling

5.2 A Brief Look at Data Types for Behavioral Modeling

5.3 Boolean Equation-Based Behavioral Models of Combinational Logic

5.4 Propagation Delay and Continuous Assignments

5.5 Latches and Level-Sensitive Circuits in Verilog

5.6 Cyclic Behavioral Models of Flip-Flops and Latches

5.7 Cyclic Behavior and Edge Detection

5.8 A Comparison of Styles for Behavioral Modeling

5.8.1 Continuous Assignment Models

5.8.2 Dataflow/RTL Models

5.8.3 Algorithm-Based Models

5.8.4 Naming Conventions: A Matter of Style

5.8.5 Simulation with Behavioral Models

5.9 Behavioral Models of Multiplexers, Encoders, and Decoders

5.10 Dataflow Models of a Linear-Feedback Shift Register

5.11 Modeling Digital Machines with Repetitive Algorithms

5.11.1 Intellectual Property Reuse and Parameterized Models

5.11.2 Clock Generators

5.12 Machines with Multicycle Operations

5.13 Design Documentation with Functions and Tasks: Legacy or Lunacy?

5.13.1 Tasks

5.13.2 Functions

5.14 Algorithmic State Machine Charts for Behavioral Modeling

5.15 ASMD Charts

5.16 Behavioral Models of Counters, Shift Registers, and Register Files

5.16.1 Counters

5.16.2 Shift Registers

5.16.3 Register Files and Arrays of Registers (Memories)

5.17 Switch Debounce, Metastability, and Synchronizers for Asynchronous Signals

5.18 Design Example: Keypad Scanner and Encoder

References

Problems

6 Synthesis of Combinational and Sequential Logic 235

6.1 Introduction to Synthesis

6.1.1 Logic Synthesis

6.1.2 RTL Synthesis

6.1.3 High-Level Synthesis

6.2 Synthesis of Combinational Logic

6.2.1 Synthesis of Priority Structures

6.2.2 Exploiting Logical Don’t-Care Conditions

6.2.3 ASIC Cells and Resource Sharing

6.3 Synthesis of Sequential Logic with Latches

6.3.1 Accidental Synthesis of Latches

6.3.2 Intentional Synthesis of Latches

6.4 Synthesis of Three-State Devices and Bus Interfaces

6.5 Synthesis of Sequential Logic with Flip-Flops

6.6 Synthesis of Explicit State Machines

6.6.1 Synthesis of a BCD-to-Excess-3 Code Converter

6.6.2 Design Example: Synthesis of a Mealy-Type NRZ-to-Manchester

Line Code Converter

6.6.3 Design Example: Synthesis of a Moore-Type NRZ-to-Manchester

Line Code Converter

6.6.4 Design Example: Synthesis of a Sequence Recognizer 284

6.7 Registered Logic

6.8 State Encoding

6.9 Synthesis of Implicit State Machines, Registers, and Counters

6.9.1 Implicit State Machines

6.9.2 Synthesis of Counters

6.9.3 Synthesis of Registers

6.10 Resets

6.11 Synthesis of Gated Clocks and Clock Enables

6.12 Anticipating the Results of Synthesis

6.12.1 Synthesis of Data Types

6.12.2 Operator Grouping

6.12.3 Expression Substitution

6.13 Synthesis of Loops

6.13.1 Static Loops without Embedded Timing Controls

6.13.2 Static Loops with Embedded Timing Controls

6.13.3 Nonstatic Loops without Embedded Timing Controls

6.13.4 Nonstatic Loops with Embedded Timing Controls

6.13.5 State-Machine Replacements for Unsynthesizable Loops

6.14 Design Traps to Avoid

6.15 Divide and Conquer: Partitioning a Design

References

Problems

7 Design and Synthesis of Datapath Controllers 345

7.1 Partitioned Sequential Machines

7.2 Design Example: Binary Counter

7.3 Design and Synthesis of a RISC Stored-Program Machine

7.3.1 RISC SPM: Processor

7.3.2 RISC SPM:ALU

7.3.3 RISC SPM: Controller

7.3.4 RISC SPM: Instruction Set

7.3.5 RISC SPM: Controller Design

7.3.6 RISC SPM: Program Execution

7.4 Design Example: UART

7.4.1 UART Operation

7.4.2 UART Transmitter

7.4.3 UART Receiver

References

Problems

8 Programmable Logic and Storage Devices 415

8.1 Programmable Logic Devices

8.2 Storage Devices

8.2.1 Read-Only Memory (ROM)

8.2.2 Programmable ROM (PROM)

8.2.3 Erasable ROMs

8.2.4 ROM-Based Implementation of Combinational Logic

8.2.5 Verilog System Tasks for ROMs

8.2.6 Comparison of ROMs

8.2.7 ROM-Based State Machines

8.2.8 Flash Memory

8.2.9 Static Random Access Memory (SRAM)

8.2.10 Ferroelectric Nonvolatile Memory

8.3 Programmable Logic Array (PLA)

8.3.1 PLA Minimization

8.3.2 PLA Modeling

8.4 Programmable Array Logic (PAL)

8.5 Programmability of PLDs

8.6 Complex PLDs (CPLDs)

8.7 Field-Programmable Gate Arrays

8.7.1 The Role of FPGAs in the ASIC Market

8.7.2 FPGA Technologies

8.7.3 XILINX Virtex FPGAs

8.8 Embeddable and Programmable IP Cores for a System-on-a-Chip (SoC)

8.9 Verilog-Based Design Flows for FPGAs

8.10 Synthesis with FPGAs

References

Related Web Sites

Problems and FPGA-Based Design Exercises

9 Algorithms and Architectures for Digital Processors 515

9.1 Algorithms, Nested-Loop Programs, and Data Flow Graphs

9.2 Design Example: Halftone Pixel Image Converter

9.2.1 Baseline Design for a Halftone Pixel Image Converter

9.2.2 NLP-Based Architectures for the Halftone Pixel Image Converter

9.2.3 Minimum Concurrent Processor Architecture for a Halftone Pixel Image Converter

9.2.4 Halftone Pixel Image Converter: Design Tradeoffs

9.2.5 Architectures for Dataflow Graphs with Feedback

9.3 Digital Filters and Signal Processors

9.3.1 Finite-Duration Impulse Response Filter

9.3.2 Digital Filter Design Process

9.3.3 Infinite-Duration Impulse Response Filter

9.4 Building Blocks for Signal Processors

9.4.1 Integrators (Accumulators)

9.4.2 Differentiators

9.4.3 Decimation and Interpolation Filters

9.5 Pipelined Architectures

9.5.1 Design Example: Pipelined Adder

9.5.2 Design Example: Pipelined FIR Filter

9.6 Circular Buffers

9.7 Asynchronous FIFOs–Synchronization across Clock Domains

9.7.1 Simplified Asynchronous FIFO

9.7.2 Clock Domain Synchronization for an Asynchronous FIFO

References

Problems

10 Architectures for Arithmetic Processors 627

10.1 Number Representation

10.1.1 Signed Magnitude Representation of Negative Integers

10.1.2 Ones Complement Representation of Negative Integers

10.1.3 Twos Complement Representation of Positive and Negative Integers

10.1.4 Representation of Fractions

10.2 Functional Units for Addition and Subtraction

10.2.1 Ripple-Carry Adder

10.2.2 Carry Look-Ahead Adder

10.2.3 Overflow and Underflow

10.3 Functional Units for Multiplication

10.3.1 Combinational (Parallel) Binary Multiplier

10.3.2 Sequential Binary Multiplier

10.3.3 Sequential Multiplier Design: Hierarchical Decomposition

10.3.4 STG-Based Controller Design

10.3.5 Efficient STG-Based Sequential Binary Multiplier

10.3.6 ASMD-Based Sequential Binary Multiplier

10.3.7 Efficient ASMD-Based Sequential Binary Multiplier

10.3.8 Summary of ASMD-Based Datapath and Controller Design

10.3.9 Reduced-Register Sequential Multiplier

10.3.10 Implicit-State-Machine Binary Multiplier

10.3.11 Booth’s Algorithm Sequential Multiplier

10.3.12 Bit-Pair Encoding

10.4 Multiplication of Signed Binary Numbers

10.4.1 Product of Signed Numbers: Negative Multiplicand,

Positive Multiplier

10.4.2 Product of Signed Numbers: Positive Multiplicand,

Negative Multiplier

10.4.3 Product of Signed Numbers: Negative Multiplicand,

Negative Multiplier

10.5 Multiplication of Fractions

10.5.1 Signed Fractions: Positive Multiplicand, Positive Multiplier

10.5.2 Signed Fractions: Negative Multiplicand, Positive Multiplier

10.5.3 Signed Fractions: Positive Multiplicand, Negative Multiplier

10.5.4 Signed Fractions: Negative Multiplicand, Negative Multiplier

10.6 Functional Units for Division

10.6.1 Division of Unsigned Binary Numbers

10.6.2 Efficient Division of Unsigned Binary Numbers

10.6.3 Reduced-Register Sequential Divider

10.6.4 Division of Signed (2s Complement) Binary Numbers

10.6.5 Signed Arithmetic

References

Problems

11 Postsynthesis Design Tasks 749

11.1 Postsynthesis Design Validation

11.2 Postsynthesis Timing Verification

11.2.1 Static Timing Analysis

11.2.2 Timing Specifications

11.2.3 Factors That Affect Timing

11.3 Elimination of ASIC Timing Violations

11.4 False Paths

11.5 System Tasks for Timing Verification

11.5.1 Timing Check: Setup Condition

11.5.2 Timing Check: Hold Condition

11.5.3 Timing Check: Setup and Hold Conditions

11.5.4 Timing Check: Pulsewidth Constraint

11.5.5 Timing Check: Signal Skew Constraint

11.5.6 Timing Check: Clock Period

11.5.7 Timing Check: Recovery Time

11.6 Fault Simulation and Manufacturing Tests

11.6.1 Circuit Defects and Faults

11.6.2 Fault Detection and Testing

11.6.3 D-Notation

11.6.4 Automatic Test Pattern Generation for Combinational Circuits

11.6.5 Fault Coverage and Defect Levels

11.6.6 Test Generation for Sequential Circuits

11.7 Fault Simulation

11.7.1 Fault Collapsing

11.7.2 Serial Fault Simulation

11.7.3 Parallel Fault Simulation

11.7.4 Concurrent Fault Simulation

11.7.5 Probabilistic Fault Simulation

11.8 JTAG Ports and Design for Testability

11.8.1 Boundary Scan and JTAG Ports

11.8.2 JTAG Modes of Operation

11.8.3 JTAG Registers

11.8.4 JTAG Instructions

11.8.5 TAP Architecture

11.8.6 TAP Controller State Machine

11.8.7 Design Example:Testing with JTAG

11.8.8 Design Example: Built-In Self-Test

References

Problems

A Verilog Primitives 851

A.1 Multiinput Combinational Logic Gates

A.2 Multioutput Combinational Gates

A.3 Three-State Logic Gates

A.4 MOS Transistor Switches

A.5 MOS Pull-Up/Pull-Down Gates

A.6 MOS Bidirectional Switches

B Verilog Keywords 863

C Verilog Data Types 865

C.1 Nets

C.2 Register Variables

C.3 Constants

C.4 Referencing Arrays of Nets or Regs

D Verilog Operators 873

D.1 Arithmetic Operators

D.2 Bitwise Operators

D.3 Reduction Operators

D.4 Logical Operators

D.5 Relational Operators

D.6 Shift Operators

D.7 Conditional Operator

D.8 Concatenation Operator

D.9 Expressions and Operands

D.10 Operator Precedence

D.11 Arithmetic with Signed Data Types

D.12 Signed Literal Integers

D.13 System Functions for Sign Conversion

2.1.1 Assignment Width Extension

E Verilog Language Formal Syntax 885

F Verilog Language Formal Syntax 887

F.1 Source text

F.2 Declarations

F.3 Primitive instances

F.4 Module and generated instantiation

F.5 UDP declaration and instantiation

F.6 Behavioral statements

F.7 Specify section

F.8 Expressions

F.9 General

G Additional Features of Verilog 913

G.1 Arrays of Primitives

G.2 Arrays of Modules

G.3 Hierarchical Dereferencing

G.4 Parameter Substitution

G.5 Procedural Continuous Assignment

G.6 Intra-Assignment Delay

G.7 Indeterminate Assignment and Race Conditions

G.8 wait STATEMENT

G.9 fork join Statement

G.10 Named (Abstract) Events

G.11 Constructs Supported by Synthesis Tools

H Flip-Flop and Latch Types 925

I Verilog-2001, 2005 927

I.1 ANSI C Style Changes

I.2 Code Management

I.3 Support for Logic Modeling

I.4 Support for Arithmetic

I.5 Sensitivity List for Event Control

I.6 Sensitivity List for Combinational Logic

I.7 Parameters

I.8 Instance Generation

J Programming Language Interface 949

K Web sites 951

L Web-Based Resources 953

Index 965

本书从逻辑族、数字系统、布尔代数和逻辑门以及组合电路等基础知识开始，接着介绍时序逻辑、ASM、可编程逻辑器件、转换器和半导体存储器等应用方面。

图2 Digital Electronics (G. K. Kharate)

本书的所有章节都以概述章节内容开始，并包括许多已解决的示例和复习问题，以增强对关键概念的理解，目录如下：

第四版中新的、更新的和扩展的主题包括：EBCDIC、格雷码、触发器的实际应用、线性和轴编码器、存储器元件和 FPGA。

图3 Digital Logic Design (Brian Holdsworth, Clive Woods)

关于故障查找的部分已扩展。新章节专门讨论数字元件和模拟电压之间的接口，目录如下：

Chapter 1: Number systems and codes

1.1 Introduction

1.2 Number systems

1.3 Conversion between number systems

1.4 Binary addition and subtraction

1.5 Signed arithmetic

1.6 Complement arithmetic

1.7 Complement representation for binary numbers

1.8 The validity of 1’s and 2’s complement arithmetic

1.9 Offset binary representation

1.10 Addition and subtraction of 2’s complement numbers

1.11 Graphical interpretation of 2’s complement representation

1.12 Addition and subtraction of 1’s complement numbers

1.13 Multiplication of unsigned binary numbers

1.14 Multiplication of signed binary numbers

1.15 Binary division

1.16 Floating point arithmetic

1.17 Binary codes for decimal digits

1.18 n-cubes and distance

1.19 Error detection and correction

1.20 The Hamming code

1.21 Gray code

1.22 The ASCII code

Problems

Chapter 2: Boolean algebra

2.1 Introduction

2.2 Boolean algebra

2.3 Derived Boolean operations

2.4 Boolean functions

2.5 Truth tables

2.6 The logic of a switch

2.7 The switch implementation of the AND function

2.8 The switch implementation of the OR function

2.9 The gating function of the AND and OR gates

2.10 The inversion function

2.11 Gate or switch implementation of a Boolean function

2.12 The Boolean theorems

2.13 Complete sets

2.14 The exclusive-OR (XOR) function

2.15 The Reed–Muller equation

2.16 Set theory and the Venn diagram

Chapter 3: Karnaugh maps and function simplification

3.2 Introduction

3.2 Minterms and maxterms

3.3 Canonical forms

3.4 Boolean functions of two variables

3.5 The Karnaugh map

3.6 Plotting Boolean functions on a Karnaugh map

3.7 Maxterms on the Karnaugh map

3.8 Simplification of Boolean functions

3.9 The inverse function

3.10 ‘Don’t care’ terms

3.11 Simplification of products of maxterms

3.12 The Quine–McCluskey tabular simplification method

3.13 Properties of prime implicant tables

3.14 Cyclic prime implicant tables

3.15 Semi-cyclic prime implicant tables

3.16 Quine–McCluskey simplification of functions containing ‘don’t care’ terms

3.17 Decimal approach to Quine–McCluskey simplification of Boolean functions

3.18 Multiple output circuits

3.19 Tabular methods for multiple output functions

3.20 Reduced dimension maps

3.21 Plotting RDMs from truth tables

3.22 Reading RDM functions

3.23 Looping rules for RDMs

3.24 Criteria for minimisation

Problems

Chapter 4: Combinational logic design principles

4.1 Introduction

4.2 The NAND function

4.3 NAND logic implementation of AND and OR functions

4.4 NAND logic implementation of sums-of-products

4.5 The NOR function

4.6 NOR logic implementation of AND and OR functions

4.7 NOR logic implementation of products-of-sums

4.8 NOR logic implementation of sums-of-products

4.9 Boolean algebraic analysis of NAND and NOR networks

4.10 Symbolic circuit analysis for NAND and NOR networks

4.11 Alternative function representations

4.12 Gate signal conventions

4.13 Gate expansion

4.14 Miscellaneous gate networks

4.15 Exclusive-OR and exclusive-NOR

4.16 Noise margins

4.17 Propagation time

4.18 Speed-power products

4.19 Fan-out

Problems

Chapter 5: Combinational logic design with MSI circuits

5.1 Introduction

5.2 Multiplexers and data selection

5.3 Available MSI multiplexers

5.4 Interconnecting multiplexers

5.5 The multiplexer as a Boolean function generator

5.6 Multi-level multiplexing

5.7 Demultiplexers

5.8 Multiplexer/demultiplexer data transmission system

5.9 Decoders

5.10 Decoder networks

5.11 The decoder as a minterm generator

5.12 Display decoding

5.13 Encoder circuit principles

5.14 Available MSI encoders

5.15 Encoding networks

5.16 Parity generation and checking

5.17 Digital comparators

5.18 Iterative circuits

Chapter 6: Latches and flip-flops

6.1 Introduction

6.2 The bistable element

6.3 The SR latch

6.4 The controlled SR latch

6.5 The controlled D latch

6.6 Latch timing parameters

6.7 The JK flip-flop

6.8 The master/slave JK flip-flop

6.9 Asynchronous controls (direct preset and clear)

6.10 1’s and 0’s catching

6.11 The master/slave SR flip-flop

6.12 The edge-triggered D flip-flop

6.13 The edge-triggered JK flip-flop

6.14 The T flip-flop

6.15 Mechanical switch debouncing

6.16 Registers

Problems

Chapter 7: Counters and registers

7.1 Introduction

7.2 The clock signal

7.3 Basic counter design

7.4 Series and parallel connection of counters

7.5 Scale-of-five up-counter

7.6 The design steps for a synchronous counter

7.7 Gray code counters

7.8 Design of decade Gray code up-counter

7.9 Scale-of-16 up/down counter

7.10 Asynchronous binary counters

7.11 Decoding of asynchronous counters

7.12 Asynchronous resettable counters

7.13 Integrated circuit counters

7.14 Cascading of IC counter chips

7.15 Shift registers

7.16 The 4-bit 7494 shift register

7.17 The 4-bit 7495 universal shift register

7.18 The 74165 parallel loading 8-bit shift register

7.19 The use of shift registers as counters and sequence generators

7.20 The universal state diagram for shift registers

7.21 The design of a decade counter

7.22 The ring counter

7.23 The twisted ring or Johnson counter

7.24 Series and parallel interconnection of Johnson counters

7.25 Shift registers with XOR feedback

7.26 Multi-bit rate multipliers

Problems

Chapter 8: Clock-driven sequential circuits

8.1 Introduction

8.2 The basic synchronous sequential circuit

8.3 Analysis of a clocked sequential circuit

8.4 Design steps for synchronous sequential circuits

8.5 The design of a sequence detector

8.6 The Moore and Mealy state machines

8.7 Analysis of a sequential circuit implemented with JK flip-flops

8.8 Sequential circuit design using JK flip-flops

8.9 State reduction

8.10 State assignment

8.11 Algorithmic state machine charts

8.12 Conversion of an ASM chart into hardware

8.13 The ‘one-hot’ state assignment

8.14 Clock skew

8.15 Clock timing constraints

8.16 Asynchronous inputs

8.17 The handshake

Problems

Chapter 9: Event driven circuits

9.1 Introduction

9.2 Design procedure for asynchronous sequential circuits

9.3 Stable and unstable states

9.4 Design of a lamp switching circuit

9.5 Races

9.6 Race free assignments

9.7 The pump problem

9.8 Design of a sequence detector

9.9 State reduction for incompletely specified machines

9.10 Compatibility

9.11 Determination of compatible pairs

9.12 The merger diagram

9.13 The state reduction procedure

9.14 Circuit hazards

9.15 Gate delays

9.16 The generation of spikes

9.17 The generation of static hazards in combinational networks

9.18 The elimination of static hazards

9.19 Design of hazard-free combinational networks

9.20 Detection of hazards in an existing network

9.21 Hazard-free asynchronous circuit design

9.22 Dynamic hazards

9.23 Function hazards

9.24 Essential hazards

Chapter 10: Instrumentation and interfacing

10.1 Introduction

10.2 Schmitt trigger circuits

10.3 Schmitt input gates

10.4 Digital-to-analogue conversion

10.5 Analogue-to-digital conversion

10.6 Flash converters

10.7 Integrating A/D converter types

10.8 A/D converter types using an embedded D/A converter

10.9 Shaft encoders and linear encoders

10.10 Sensing of motion

10.11 Absolute encoders

10.12 Conversion from Gray code to base 2

10.13 Petherick code

10.14 Incremental encoders

10.15 Open collector and tri-state gates

10.16 Use of open collector gates

10.17 Use of tri-state buffers and gates

10.18 Other interfacing components

Problems

Chapter 11: Programmable logic devices

11.1 Introduction

11.2 Read only memory

11.3 ROM timing

11.4 Internal ROM structure

11.5 Implementation of Boolean functions using ROMs

11.7 Memory addressing

11.8 Design of sequential circuits using ROMs

11.9 Programmable logic devices (PLDs)

11.10 Programmable gate arrays (PGAs)

11.11 Programmable logic arrays (PLAs)

11.12 Programmable array logic (PAL)

11.13 Programmable logic sequencers (PLSs)

11.14 Field programmable gate arrays (FPGAs)

11.15 Xilinx field programmable gate arrays

11.16 Actel programmable gate arrays

11.17 Altera erasable programmable logic devices

Problems

Chapter 12: Arithmetic circuits

12.1 Introduction

12.2 The half adder

12.3 The full adder

12.4 Binary subtraction

12.5 The 4-bit binary full adder

12.6 Carry look-ahead addition

12.7 The 74283 4-bit carry look-ahead adder

12.8 Addition/subtraction circuits using complement arithmetic

12.9 Overflow

12.10 Serial addition and subtraction

12.11 Accumulating adder

12.12 Decimal arithmetic with MSI adders

12.13 Adder/subtractor for decimal arithmetic

12.14 The 7487 true/complement unit

12.15 Arithmetic/logic unit design

12.16 Available MSI arithmetic/logic units

12.17 Multiplication

12.18 Combinational multipliers

12.19 ROM implemented multiplier

12.20 The shift and add multiplier

12.21 Available multiplier packages

12.22 Signed arithmetic

12.23 Booth’s algorithm

12.24 Implementation of Booth’s algorithm

Chapter 13: Fault diagnosis and testing

13.1 Introduction

13.2 Fault detection and location

13.3 Gate sensitivity

13.4 A fault test for a 2-input AND gate

13.5 Path sensitisation

13.6 Path sensitisation in networks with fan-out

13.7 Undetectable faults

13.8 Bridging faults

13.9 The fault detection table

13.10 Two-level circuit fault detection in AND/OR circuits

13.11 Two-level circuit fault detection in OR/AND circuits

13.12 Boolean difference

13.13 Compact testing techniques

13.14 Signature analysis

13.15 The scan path testing technique

13.16 Designing for testability