【提问】这篇代码仿真32行报错,错误点在哪,给这篇代码加按键和数码管怎么加-FPGA常见问题社区-FPGA CPLD-ChipDebug

提问这篇代码仿真32行报错,错误点在哪,给这篇代码加按键和数码管怎么加

module counter(DIN,CLK,CLR,ENABLE,UPCNTCTRL,DOWNCNTCTRL,COUT,R,P);
input CLK,CLR,ENABLE,UPCNTCTRL,DOWNCNTCTRL;
input [7:0]DIN;
output [7:0]COUT;
output R,P;
reg [7:0]COUT;
reg R,P;
always @(posedge CLK or CLR or ENABLE)
begin
if(CLR)
begin
COUT=0;
P=0;
R=0;
end
else if (ENABLE==1)
begin
COUT<=DIN;
end
else
begin
if(UPCNTCTRL)
begin
COUT<=COUT+1;
end
else if(DOWNCNTCTRL)
begin
COUT<=COUT-1;
end
end
end
always @(posedge CLK)
begin
if(COUT==’hFF && UPCNTCTRL==1)
begin
R=1;
end
else
begin
R=0;
end
if(COUT==’h0 && DOWNCNTCTRL==1)
begin
P=1;
end
else
begin
P=0;
end
end
endmodule

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