为什么我在Arria 10 SerialLite 3流设计中看到了设置时序违规？

6年前发布

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由于QuartusPrime®软件版本16.1.2及更早版本中的问题，您的Arria®10SerialLite™III内核可能会在“ pld_10g_tx_pempty_reg node ”和“ altera标准同步器stdsync_txpempty | din_s1 ”之间的路径中出现设置时序违规下面：

从节点：seriallite_iii_streaming：seriallite_iii_streaming_inst | seriallite_iii_streaming_seriallite_iii_a10_161_jvvqjaa：seriallite_iii_streaming | interlaken_native_wrapper_duplex_seriallite_iii_streaming_seriallite_iii_a10_161_zgsou7q：A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex | seriallite_iii_streaming_seriallite_iii_a10_161_zgsou7q：DUPLEX_WRAPPER.interlaken_inst | seriallite_iii_streaming_altera_xcvr_native_a10_161_koe2tsa：native_ilk_wrapper | twentynm_xcvr_native：g_xcvr_native_insts [5] .twentynm_xcvr_native_inst | twentynm_xcvr_native_rev_20nm5es：twentynm_xcvr_native_inst | twentynm_pcs_rev_20nm5es：inst_twentynm_pcs | gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs〜pld_10g_tx_pempty_reg。 REG
到节点：seriallite_iii_streaming：seriallite_iii_streaming_inst | seriallite_iii_streaming_seriallite_iii_a10_161_jvvqjaa：seriallite_iii_streaming | interlaken_native_wrapper_duplex_seriallite_iii_streaming_seriallite_iii_a10_161_zgsou7q：A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex | altera_std_synchronizer_nocut：pcs_lanes [5] .stdsync_txpempty | din_s1
启动时钟： seriallite_iii_streaming_inst | seriallite_iii_streaming | g_xcvr_native_insts [*] | tx_pma_clk
锁存时钟： seriallite_iii_streaming_inst | seriallite_iii_streaming | g_xcvr_native_insts [0] | tx_pma_clk

解决/修复方法

要解决此问题，用户必须修改生成的ip .sdc文件（ seriallite_iii_streaming * .sdc ）。

原始的.sdc约束如下：

set_max_skew -摘自[get_keepers {* $ MODULE_NAME * | * interlaken_native_wrapper_duplex | * | twentynm_xcvr_native_inst | twentynm_xcvr_native_inst | inst_twentynm_pcs | inst_twentynm_hssi_10g_tx_pcs〜pld_10g_tx_pempty_reg.reg}] -to [get_keepers {* $ MODULE_NAME * | interlaken_native_wrapper_duplex | stdsync_txpempty | din_s1}] -get_skew_value_from_clock_period src_clock_period – skew_value_multiplier 0.85

set_net_delay -摘自[get_keepers {* $ MODULE_NAME * | * interlaken_native_wrapper_duplex | * | twentynm_xcvr_native：g_xcvr_native_insts [*] twentynm_xcvr_native_inst | twentynm_xcvr_native_rev_20nm4：twentynm_xcvr_native_inst | twentynm_pcs_rev_20nm4：inst_twentynm_pcs | gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs〜pld_10g_tx_pempty_reg.reg}] -to [get_keepers {* $ MODULE_NAME * | interlaken_native_wrapper_duplex _ *：A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex | altera_std_synchronizer_nocut：pcs_lanes [*] .stdsync_txpempty | din_s1}] -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.85

set_max_delay -摘自[get_keepers {* $ MODULE_NAME * | * interlaken_native_wrapper_duplex | * | twentynm_xcvr_native：g_xcvr_native_insts [*] twentynm_xcvr_native_inst | twentynm_xcvr_native_rev_20nm4：twentynm_xcvr_native_inst | twentynm_pcs_rev_20nm4：inst_twentynm_pcs | gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs〜pld_10g_tx_pempty_reg.reg}] -to [get_keepers {* $ MODULE_NAME * | interlaken_native_wrapper_duplex _ *：A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex | altera_std_synchronizer_nocut：pcs_lanes [*] .stdsync_txpempty | din_s1}] 100

set_min_delay -摘自[get_keepers {* $ MODULE_NAME * | * interlaken_native_wrapper_duplex | * | twentynm_xcvr_native：g_xcvr_native_insts [*] twentynm_xcvr_native_inst | twentynm_xcvr_native_rev_20nm4：twentynm_xcvr_native_inst | twentynm_pcs_rev_20nm4：inst_twentynm_pcs | gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs〜pld_10g_tx_pempty_reg.reg}] -to [get_keepers {* $ MODULE_NAME * | interlaken_native_wrapper_duplex _ *：A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex | altera_std_synchronizer_nocut：pcs_lanes [*]。stdsync_txpempty | din_s1}] -100

应替换为以下限制：

set inst_xcvr_list [get_entity_instances twentynm_xcvr_native]

foreach each_xcvr_inst \ $ inst_xcvr_list {

if {[string equal“quartus_sta”\ $ :: TimeQuestInfo（nameofexecutable）]} {

set_max_skew -from [get_keepers \ $ each_xcvr_inst * | * inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] -to [get_keepers {* stdsync_txpempty | din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.85

}

set_net_delay -from [get_keepers \ $ each_xcvr_inst * | * inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] -to [get_keepers {* stdsync_txpempty | din_s1}] -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.85

set_max_delay -from [get_keepers \ $ each_xcvr_inst * | * inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] -to [get_keepers {* stdsync_txpempty | din_s1}] 100

set_min_delay -from [get_keepers \ $ each_xcvr_inst * | * inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] -to [get_keepers {* stdsync_txpempty | din_s1}] -100

}

从QuartusPrime®软件的软件版本17.0开始修复此问题。

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