针对Arria V或Cyclone V器件的RapidIO IP Core 5.0 Gbaud变体的编译警告-Altera-Intel社区-FPGA CPLD-ChipDebug

针对Arria V或Cyclone V器件的RapidIO IP Core 5.0 Gbaud变体的编译警告

编译面向Arria V或Cyclone V器件的5.0 Gbaud RapidIO IP内核变体时,会出现以下警告:

Warning (332174): Ignored filter at rio.sdc(104): *rio*riophy_xcvr|clk_div_by_two could not be matched with a net Warning (332049): Ignored create_generated_clock at rio.sdc(104): *rio*riophy_xcvr|clk_div_by_two could not be matched with a net Warning (332049): Ignored create_generated_clock at rio.sdc(104): Argument <targets> is an empty collection Info (332050): create_generated_clock -name clk_div_by_two_rio - source [get_nets *rio_rio_inst*pld8gtxclkout] -divide_by 2 [get_nets *rio*riophy_xcvr|clk_div_by_two] Warning (332174): Ignored filter at rio.sdc(167): clk_div_by_two_rio could not be matched with a clock

解决/修复方法

此问题没有设计影响。您可以忽略这些警告。

此问题已在RapidIO MegaCore功能的13.0版中得到修复。

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