无法为Stratix IV或Stratix V生成DDR3 RDIMM IP,RC8-RC15​​设置为非零值-Altera-Intel社区-FPGA CPLD-ChipDebug

无法为Stratix IV或Stratix V生成DDR3 RDIMM IP,RC8-RC15​​设置为非零值

此问题会影响DDR3产品。

如果为DDR3 RDIMM控制字的任何RC8-RC15​​字段指定非零值,则IP生成将失败,并显示以下错误:

Error: integer value too large to represent.

解决/修复方法

此问题的解决方法是修改uniphy_gen.tcl文件中的代码。按着这些次序:

  1. ip/altera/alt_mem_if/alt_mem_if_tcl_packages/gen/�目录中,在编辑器中打开uniphy_gen.tcl文件。
  2. uniphy_gen.tcl文件中,搜索以下文本注释:
  3. # Need to split the 64-bit RDIMM configuration word into 2 32-bit words for the sake of C-code�

  4. 在文本注释的位置,替换以下现有代码:
  5. if {([string compare -nocase "DDR3"] == 0) && } { # Need to split the 64-bit RDIMM configuration word into 2 32-bit words for the sake of C-code set rdimm_config_dec [ expr 0x[get_parameter_value RDIMM_CONFIG] ] set rdimm_config_high [ format "0x%X" [ expr >> 32 ] ] set rdimm_config_low [ format "0x%X" [ expr & 0xFFFFFFFF ] ] append sw_macros " -DRDIMM_CONFIG_WORD_LOW=" append sw_macros " -DRDIMM_CONFIG_WORD_HIGH=" }

    使用以下新代码:

    if {([string compare -nocase "DDR3"] == 0) && } { # Need to split the 64-bit RDIMM configuration word into 2 32-bit words for the sake of C-code set rdimm_config_str [ get_parameter_value RDIMM_CONFIG ] set rdimm_config_low "0x[ string range end-7 end ]" # Handle two halves of 16-byte string independently if {([string length ] > 8)} { set rdimm_config_high "0x[ string range end-15 end-8 ]" } else { set rdimm_config_high "0x0" } append sw_macros " -DRDIMM_CONFIG_WORD_LOW=" append sw_macros " -DRDIMM_CONFIG_WORD_HIGH=" }

此问题将在以后的版本中修复。

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