Arria V以太网MAC示例设计中的10GBASE-R PHY IP核保持时间违规

解决方法是将以下Synopsys设计约束（SDC）添加到您的设计中：

如果{$ :: TimeQuestInfo（nameofexecutable）== “文件quartus_fit”} {set_min_delay -to {altera_eth_10g_mac_base_r_av：SUT | altera_eth_10g_mac_base_r_av_eth_10g_design_example_0：eth_10g_design_example_0 | altera_xcvr_10gbaser：altera_10gbaser | av_xcvr_10gbaser_nr：av_xcvr_10gbaser_nr_inst | av_xcvr_10gbaser_native：CH [0] .av_xcvr_10gbaser_native_inst | alt_10gbaser_pcs：av_10gbaser_soft_pcs_inst | altera_10gbaser_phy_pcs_10g_top ：pcs_10g_top_0 | altera_10gbaser_phy_pcs_10g：pcs_10g_0 | altera_10gbaser_phy_tx_top：tx_top | altera_10gbaser_phy_clockcomp：tx_altera_10gbaser_phy_clockcomp | altera_10gbaser_phy_async_fifo_fpga：altera_10gbaser_phy_async_fifo_fpga | DCFIFO：dcfifo_componenet * fifo_ram *} 1.0 set_min_delay -from {altera_eth_10g_mac_base_r_av：SUT | altera_eth_10g_mac_base_r_av_eth_10g_design_example_0：eth_10g_design_example_0 | altera_xcvr_10gbaser：altera_10gbaser | av_xcvr_10gbaser_nr：av_xcvr_10gbaser_nr_inst | av_xcvr_10gbaser_native：CH [0] .av_xcvr_10gbaser_native_inst | alt_10gbaser_pcs：av_10gbaser_soft_pcs_inst | altera_10gbaser _phy_pcs_10g_top：pcs_10g_top_0 | altera_10gbaser_phy_pcs_10g：pcs_10g_0 | altera_10gbaser_phy_tx_top：tx_top | altera_10gbaser_phy_clockcomp：tx_altera_10gbaser_phy_clockcomp | altera_10gbaser_phy_async_fifo_fpga：altera_10gbaser_phy_async_fifo_fpga | DCFIFO：dcfifo_componenet * fifo_ram *}} 1.0

您还可以通过从SDC路径“altera_eth_10g_mac_base_r_av”中删除以下文本，将此解决方法用于10GBASE-R PHY IP内核。