The UHD HDMI 2.0 Video Format Conversion Design Example requires the
following hardware:
• Intel Arria 10 GX FPGA Development Kit, including the DDR4 Hilo
Daughter Card
• Bitec HDMI 2.0 FMC daughter card (revision 11)
• HDMI 2.0 source that produces up to 3840x2160p60 video without
HDCP encryption
• HDMI 2.0 sink that displays up to 3840x2160p60 video
• Intel recommends the use of VESA certified HDMI 2.0 cables.
The design version requires the following software:
• Windows or Linux OS
• The Intel Quartus Prime Pro Design Suite v20.4 that includes:
— Intel Quartus Prime Pro Edition
— Platform Designer
— Nios II EDS
— Intel FPGA IP Library (including the Video and Image
Processing Suite)
The design only works with this version of Intel Quartus Prime.
1 This specification provides a flexible, low-cost, High-Speed serial interface solution for communication
2 interconnection between components inside a mobile device. Traditionally, these interfaces are CMOS
3 parallel busses at low bit rates with slow edges for EMI reasons. The D-PHY solution enables significant
4 extension of the interface bandwidth for more advanced applications. The D-PHY solution can be realized
5 with very low power consumption.
10
Alliance application or protocol level specifications. This includes the physical interface, electrical interface, 11
low-level timing and the PHY-level protocol. The goal has been to define a C-PHY high-speed interface that 12
can coexist on the same pins as the MIPI D-PHY interface. These functional areas taken together are known 13
as C-PHY.
This specification provides a flexible, low-cost, High-Speed serial interface solution for communication 287
interconnection between components inside a mobile device. Traditionally, these interfaces are CMOS 288
parallel busses at low bit rates with slow edges for EMI reasons. The D-PHY solution enables significant 289
extension of the interface bandwidth for more advanced applications. The D-PHY solution can be realized 290
with very low power consumption.
The Display Serial Interface Specification defines protocols between a host processor and peripheral devices 2 that adhere to MIPI Alliance Specifications for mobile device interfaces. The DSI Specification builds on
3 existing specifications by adopting pixel formats and command set defined in [MIPI02], [MIPI03], and
4 [MIPI01].
