未找到相关的寄存器进行配置,实现跳转
hitless的功能就是保证在加载过程中 某些重要的固定电平不变 否则会影响电源芯片以及DSP芯片的正常功能
不只是XO3有,LATTCIE的其它系列的CPLD和FPGA也都有这个功能。
我看了pyznq的代码,你用spi_open_device这上函数打开应该就可以实现slave,
spi spi_open_device(unsigned int device) {
int status;
u16 dev_id;
unsigned int base_address;
u32 control;
if (device < XPAR_XSPI_NUM_INSTANCES) {
dev_id = (u16) device;
}
else {
int found = 0;
for (u16 i = 0; i < XPAR_XSPI_NUM_INSTANCES; ++i) {
if (XSpi_ConfigTable[i].BaseAddress == device) {
found = 1;
dev_id = i;
break;
}
}
if (!found)
return -1;
}
status = XSpi_Initialize(&xspi[dev_id], dev_id);
if (status != XST_SUCCESS) {
return -1;
}
base_address = xspi[dev_id].BaseAddr;
// Soft reset SPI
XSpi_WriteReg(base_address, XSP_SRR_OFFSET, 0xA);
// Master mode
control = XSpi_ReadReg(base_address, XSP_CR_OFFSET);
// Master Mode
control |= XSP_CR_MASTER_MODE_MASK;
// Enable SPI
control |= XSP_CR_ENABLE_MASK;
// Slave select manually
control |= XSP_INTR_SLAVE_MODE_MASK;
// Enable Transmitter
control &= ~XSP_CR_TRANS_INHIBIT_MASK;
// Write configuration word
XSpi_WriteReg(base_address, XSP_CR_OFFSET, control);
return (spi) dev_id;
}
1.Xilinx ISE 查看子模块资源消耗(我的是14.7,可能跟你的版本略有差异)
先选中顶层,然后在流程的MAP这里右键打开属性对话框,勾上detail, 然后在报告的13项里面查看
2.xilinx有一个专门的文档工具,在这里
https://www.xilinx.com/support/documentation-navigation/overview.html